Introduction
The author has been involved in embedded software development for nearly five years, primarily using microcontrollers from the ARM Cortex-M series. During these five years, thanks to the existence of C language compilers, I have been able to develop without delving into assembly language. However, it seems I have missed out on some aspects of the beauty of compilers and CPUs. Therefore, I decided to spend my weekends exploring the wonders of the ARM CPU architecture and the mysteries of C language compilers through research, hands-on experiments, and conclusions drawn from them. (I personally disagree with the teaching methods of microcomputer principles courses in schools.)
1. ARM CPU Architecture
The ARM CPU architecture[1] is a family of Reduced Instruction Set Computing (RISC) architectures used for computer processors. It is the most widely used processor architecture in the world, with billions of ARM-based devices shipped each year, ranging from sensors, wearable devices, smartphones, to supercomputers.
The ARM CPU architecture is based on a RISC instruction set, which includes:
- A unified register file, where instructions are not limited to specific registers;
- A load/store architecture, where data processing occurs only on register contents, not directly on memory contents;
- Simple addressing modes, where all load or store modes are determined solely by register contents and instruction fields.
Depending on different application scenarios, the ARM CPU architecture is divided into:
| Architecture Definition | Use Cases | Implementations (Processor Cores) |
|---|---|---|
| A Series | Complex computer applications (servers, networking devices, smartphones, TVs) | Cortex-A, Neoverse |
| R Series | Used in scenarios requiring real-time responses (strict security applications, applications requiring deterministic responses, autonomous driving) | Cortex-R |
| M Series | Devices where power consumption and size are critical, especially embedded and IoT devices, such as small sensors, communication modules, smart home products, etc. | Cortex-M |
In this series of articles, we will primarily explore the Cortex-M cores, without considering the Cortex-A and Cortex-R series.
2. Cortex-M Cores
The Cortex-M processor family is based on the ARM M architecture definition, providing low-latency and highly deterministic operations for embedded systems. The main Cortex-M series cores are shown in the figure below:
From the figure, we can see:
1. The Cortex-M0, Cortex-M0+, and Cortex-M1 series cores use the Armv6-M architecture, while the commonly used Cortex-M3, Cortex-M4, and Cortex-M7 series cores use the Armv7-M architecture. The Cortex-M23 series uses the Armv8-M Baseline architecture, and the Cortex-M33, Cortex-M33P, and Cortex-M55 series use the Armv8-M Mainline architecture.
2. Starting from the Cortex-M23 series, the Cortex-M cores include TrustZone features.
3. The Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M35P, and Cortex-M55 series include Digital Signal Processing (DSP) extensions.
4. The Cortex-M33 and Cortex-M55 series include ARM custom instructions.
5. The Cortex-M33, Cortex-M35P, and Cortex-M55 series have coprocessor interfaces.
Next, we will explore each of these cores in detail.
1. Cortex M0
The Cortex M0[2] processor is one of ARM’s smallest processors, characterized by its compact size, aimed at enabling developers to achieve 32-bit performance at an 8-bit price point.
The Cortex M0 processor uses the AHB-Lite bus, has a three-stage pipeline, and supports a subset of the Thumb/Thumb-2 instruction set.
2. Cortex M0+
The Cortex M0+[3] processor builds on the Cortex M0 processor, further reducing power consumption and enhancing performance. The Cortex M0+ processor uses the AMBA AHB-Lite bus, has a two-stage pipeline, and supports a subset of the Thumb/Thumb-2 instruction set.
3. Cortex M1
The Cortex M1[4] is the first processor designed specifically for implementation on FPGAs. It uses the AMBA AHB-Lite bus, has a three-stage pipeline, and supports a subset of the Thumb/Thumb-2 instruction set.
4. Cortex M3
The Cortex-M3[5] processor is designed for high-performance, low-cost platforms, including automotive body systems, industrial control systems, wireless networks, sensors, etc. It uses three AMBA AHB-Lite buses (Harvard architecture), has a three-stage pipeline, supports a subset of the Thumb/Thumb-2 instruction set, and supports 8 to 256 priority levels.
5. Cortex M4
The Cortex-M4[6] processor is an efficient embedded processor that uses three AMBA AHB-Lite buses (Harvard architecture), has a three-stage pipeline, supports a subset of the Thumb/Thumb-2 instruction set, and supports 8 to 256 priority levels. Compared to the Cortex-M3, it adds DSP extensions and an optional single-precision floating-point unit.
6. Cortex M7
The Cortex M7[7] processor is a high-performance, energy-efficient processor with a six-stage superscalar pipeline, supports the Thumb/Thumb-2 instruction set, supports 8 to 256 priority levels, and includes DSP extensions and an optional single-precision floating-point unit. It uses one 64-bit AMBA4 AXI bus, one 32-bit AHB peripheral interface, and one 32-bit AMBA AHB slave interface for external host access to TCM memory, and features instruction cache, data cache, instruction TCM, and data TCM.
7. Cortex M23
The Cortex M23[8] processor is a very simple processor, making it an ideal choice for most IoT and embedded applications requiring security, featuring TrustZone.
The Cortex-M23 uses the Armv8-M baseline architecture, has a two-stage pipeline, uses the AMBA 5 AHB bus, supports a subset of the Thumb/Thumb-2 instruction set, and supports four priority levels. It also adds instruction support for hardware single-cycle multiplication (32×32) and fast division (32/32).
8. Cortex M33
The Cortex-M33[9] is suitable for embedded and IoT applications requiring effective security or digital signal control. The Cortex-M33 offers many optional features, including DSP extensions, TrustZone security features for hardware-enforced isolation, a coprocessor interface, memory protection units, and floating-point units.
The Cortex-M33 uses the Armv8-M Mainline architecture, has a three-stage pipeline, uses two AMBA5 AHB buses (Harvard architecture), supports the Thumb/Thumb-2 instruction set, supports 8 to 256 interrupt priority levels, optional TrustZone for Armv8-M support, and DSP extensions with optional DSP/SIMD instructions, and optional coprocessor interface support.
Recommended reading: A deep dive into the features of Cortex-M23/33 by a knowledgeable author[10].
9. Cortex M35P
The Cortex-M35P[11] processor uses TrustZone for Armv8-M, featuring hardware security and optional software isolation features. For embedded developers seeking to prevent physical tampering and achieve higher levels of security certification, ARM offers the Cortex-M35P processor.
The Cortex-M35P uses the Armv8-M Mainline architecture, has a three-stage pipeline, uses two AMBA5 AHB buses (Harvard architecture), supports the Thumb/Thumb-2 instruction set, supports 8 to 256 interrupt priority levels, has optional coprocessor interface support, TrustZone for Armv8-M support, DSP support, and features physical security with built-in protection against invasive and non-invasive attacks.
10. Cortex M55
The latest generation of Cortex M series processors is the Cortex M55.
The Cortex-M55[12] is the first processor based on the Armv8.1-M architecture, utilizing ARM Helium technology (MVE, M-series vector extension), bringing enhanced machine learning and signal processing performance to the next generation of small embedded devices, including wearable devices and smart voice devices.
The Cortex-M55 features a four-stage pipeline, uses the AMBA 5 AXI5 64-bit host bus, has optional 64-bit coprocessor interface support, optional TrustZone support, and optional Helium technology support, with DSP extensions supporting 32-bit DSP/SIMD instruction extensions.
Conclusion
After getting to know the members of the Cortex-M family, it is evident that ARM Cortex-M is increasingly focusing on security and AI capabilities. This also provides us with a direction for development; the future of IoT will not be limited to simply connecting to cloud platforms to report data, but will also enhance the security capabilities and AI capabilities of IoT devices. After all, hardware devices facing intrusion is far more terrifying than a computer virus. If edge AI processing capabilities are significantly improved, data processing can be completed directly at the terminal without consuming unnecessary cloud computing power.
Thus, the first stop of the ARM exploration journey comes to an end! See you at the next stop!
Note: All images in this article are sourced from ARM.
References
ARM CPU Architecture:https://developer.arm.com/architectures/cpu-architecture
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