Background Introduction
In recent years, with the rise of compute-intensive fields such as artificial intelligence and financial data analysis, heterogeneous computing has gained increasing attention. Heterogeneous computing refers to a computing method that uses a system composed of computing units with different types of instruction sets and architectures. The mainstream heterogeneous parallel computing platforms are X86+GPU (Graphics Processing Unit) and X86+FPGA (Field-Programmable Gate Array). This article mainly explores the heterogeneous computing method of CPU cooperating with FPGA.
The traditional FPGA development method uses hardware description languages Verilog/VHDL, which are difficult to develop. In order to achieve a CPU/GPU-like development and operating experience on FPGA, the two major FPGA manufacturers Xilinx and Altera have launched their respective compilers SDAccel and Altera SDK optimized for high-level languages. This study is implemented in the cloud SDAccel environment provided by Nimbix, an official partner of Xilinx, using OpenCL (Open Computing Language).
Research Content
This study implements a binary tree option pricing algorithm on FPGA using OpenCL.
The implementation framework is as follows:
During the experiment, it was found that although OpenCL supports double pown(double,int), the results of this function on FPGA differ from those calculated on CPU. When the step size STEP=512, the option pricing result on FPGA can only maintain three significant digits of precision compared to the CPU calculation. Therefore, in this experiment, the calculation of all node futures prices at the STEP step of the binary tree is completed jointly by CPU and FPGA.
The development environment is as follows:
Research Results
This study verified that the CPU calculation results and FPGA software simulation results are the same for the binary tree option pricing algorithm with step sizes of 32, 64, 128, 256, 512, and 1024. Due to the long time required for hardware simulation and board-level testing, only the step size of 32 was verified. The futures price was 406.3, the option strike price was 330, the volatility was 0.3705583, the remaining days to expiration were 22, and the interest rate was 0.0531. The calculated result for a single option on FPGA was 76.176249.
During the experiment, it was found that developing FPGA using high-level languages has the following advantages:
1) Xilinx provides OpenCL development libraries, which are easy to call;
2) The kernel functions running on FPGA support OpenCL development and also support C/C++ development, making it low-cost for software developers to learn;
3) SDAccel supports gdb debugging and printf() print debugging (only applicable to OpenCL-based kernel functions);
4) Setting the workgroup size to reqd_work_group_size(1, 1, 1) allows for a C/C++ experience in writing OpenCL kernels, and Xilinx’s optimization measures can be directly applied to kernel performance optimization;
5) The advantage of SDAccel is that it shields the underlying hardware drivers, allowing developers to gain a software development experience on FPGA, which is also the biggest difference between SDAccel and Vivado HLS, as the kernel functions running on FPGA are still compiled through Vivado HLS.
This article only verifies the feasibility of developing FPGA using high-level languages, and there is still much optimization work to be done. This article aims to provide a new perspective for software developers to conduct preliminary research on using FPGA for algorithm acceleration, and colleagues interested in this are welcome to communicate together.
References
1) ug1023-sdaccel-user-guide.pdf
2) ug1164-sdaccel-platform-development.pdf
3) ug1207-sdaccel-performance-optimization.pdf
4) ug1240-sdaccel-nimbix-getting-started.pdf
