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MCU, MPU, SoC, CPU
This article provides a detailed analysis of the differences, classification criteria, and typical examples of MCU (Microcontroller Unit), MPU (Microprocessor Unit), CPU (Central Processing Unit), SoC (System on Chip), as well as the concepts of “processor” and “microcontroller”.
Core Concepts and Hierarchical Relationships
1.CPU (Central Processing Unit)
Definition: This is the core component of a computer or electronic device. It is the brain that executes instructions, performs arithmetic and logic operations, and controls data flow. The CPU is responsible for running the core logic of programs and operating systems.
Characteristics: It only contains an ALU, registers, and a control unit, and does not include memory, peripherals, or storage.
Hierarchy: The CPU is an essential core component within MCUs and MPUs. It cannot operate independently and requires external memory, storage, clock, power management, etc.
Key Features: Instruction set architecture, clock frequency, core count, cache size, power consumption. Common architectures include ARM, x86, PowerPC, RISC-V, MIPS, etc.
2.Processor
Definition: This is a very broad and sometimes vague term. It usually refers to the CPU, but in a broader context, it may also refer to a system-on-chip (SoC) that includes a CPU core and other coprocessors (such as GPU, NPU, DSP) or specific acceleration modules.
Hierarchy: It can be seen as a higher-level concept of the CPU or a general term for any unit that performs processing tasks (CPU, GPU, DSP, etc.). When we say “mobile processor” or “server processor,” we usually refer to the entire SoC (which includes CPU, GPU, NPU, memory controller, IO controller, etc.).
3.MCU (Microcontroller Unit)
Definition: A highly integrated chip that integrates a CPU core, memory (RAM), storage (usually Flash/ROM), clock circuits, and a rich set of input/output peripheral interfaces on a single chip.
Core Idea: “System on Chip”. The design goal is to allow developers to build a complete, function-specific embedded control system using just one chip (plus necessary external passive components).
Main Features:
- • High integration: CPU + RAM + Flash/ROM + various peripherals (such as GPIO, UART, SPI, I2C, ADC, DAC, PWM, Timers, USB, CAN, Ethernet PHY/MAC, etc.) are all on one chip.
- • Low power consumption: Typically designed for low-power applications, many have multiple sleep modes.
- • Low cost: Optimized for high-volume, cost-sensitive applications.
- • Strong real-time performance: Typically runs real-time operating systems or no operating system (bare metal), directly controlling hardware with fast response times.
- • Relatively low clock frequency: Usually in the range of a few MHz to several hundred MHz (recent high-performance MCUs can reach GHz).
- • Small on-chip memory: ROM/RAM capacity ranges from a few KB to several MB.
- • Moderate pin count: Various packaging forms, from very few pins (8-16) to hundreds of pins.
- • Typical applications: Appliance control (washing machines, microwaves), automotive electronics (ECU, body control), industrial automation (sensors, PLC), consumer electronics (remote controls, keyboards, mice), IoT node devices, etc.
4.MPU (Microprocessor Unit)
Definition: Essentially a more powerful CPU core (or core cluster). The key difference from MCU is that: MPUs typically do not integrate primary program storage (such as Flash) and data storage (such as RAM) on-chip.
Core Idea: “Powerful computing capability”. The design goal is to provide strong general-purpose computing power, relying on external components (additional chips) to form a complete system.
Main Features:
- • Low integration (relative to MCU): Mainly high-performance CPU cores (possibly multi-core), large capacity high-speed caches (L1/L2/L3 Cache). Does not include primary program storage and data storage.
- • High performance: High clock frequency (usually in the GHz range), powerful computing capability.
- • High power consumption: Performance leads to higher power consumption.
- • High cost (system level): Although the price of MPUs varies widely, they require expensive external DDR memory, large capacity storage (eMMC, SSD), making the overall system cost high.
- • Requires external components: Must be paired with external RAM (such as DDR3/DDR4/LPDDR), external storage (such as eMMC, NAND Flash, SSD), and complex peripheral interface controllers (through chipsets or integrated in SoC IP) to function.
- • Large on-chip memory (Cache): Has multi-level caches at the MB level.
- • Runs operating systems: Typically runs complex operating systems, such as Linux, Android, Windows.
- • High pin count: Complex packaging, high pin count (hundreds to thousands), used to connect high-speed memory buses and various high-speed interfaces.
- • Typical applications: Application processors for smartphones/tablets, personal computer/server CPUs, main control for network routers/switches, high-performance industrial computers, high-end in-vehicle infotainment systems, etc.
5.SoC (System on Chip)
Definition: A superset chip that integrates CPU + GPU + NPU + memory controller + peripherals, etc. Relationship with MCU/MPU:
- • MCU is a lightweight SoC;
- • MPU often serves as the core of SoC (for example, mobile SoCs contain Cortex-A series MPUs).
- • Key Features: Highly heterogeneous integration, typical examples include Apple M2, Snapdragon 8 series.
Impact of MMU (Memory Management Unit)
- • Function: Implements virtual memory management (address translation, memory protection).
- • Impact on classification:
Chip Type MMU Existence Impact MCU Usually none (some high-end models optional) Can only run RTOS or bare metal, cannot run Linux MPU Must have Supports virtual memory, can run Linux/Android, etc. CPU Core Depends on architecture (e.g., Cortex-A has it, Cortex-M does not) Determines whether it can be used for MPU/complex systems
🔍 MMU cannot solely determine classification:
- • Having an MMU ≠ must be an MPU (e.g., Cortex-M7 has an optional MMU but is still classified as MCU);
- • Not having an MMU ≠ must be an MCU (e.g., some high-performance RISC-V cores without MMU can be used for custom MPUs).
How to Distinguish and Determine Whether a Chip is an MCU or MPU
To determine which category a chip belongs to, refer to its official datasheet and reference manual. Focus on the following points:
1.On-chip memory (RAM and Flash) existence and size
- • MCU: Clearly includes on-chip SRAM (for data) and on-chip Flash/ROM/OTP (for storing program code), and the documentation usually specifies the exact capacity (e.g., 128KB Flash, 32KB SRAM). This is a hallmark feature of MCUs.
- • MPU: Typically does not include primary on-chip Flash/ROM for program storage (may have a small Boot ROM), nor primary on-chip SRAM (though it may have large Cache). The documentation will emphasize the need for external DDR memory and large capacity storage (such as eMMC).
2.Peripheral integration level
- • MCU: Integrates a large number of common peripheral controllers (GPIO, UART, SPI, I2C, ADC, DAC, PWM, Timers, USB, CAN, etc.), allowing developers to directly manipulate these peripheral pins.
- • MPU: May also integrate some high-speed peripheral controllers (such as PCIe, SATA, USB 3.x, Ethernet MAC), but the number is relatively small (focusing on high-speed interfaces). Many general-purpose low-speed peripherals need to be implemented by connecting external chips (such as dedicated I/O expansion chips or associated chipsets). The documentation will describe its external memory interfaces (such as DDR Controller) and high-speed IO interfaces.
3.System requirements and complexity
- • MCU: System design is relatively simple. A single MCU chip + a few external passive components (resistors, capacitors, oscillators) + sensors/actuators can usually form a minimal system.
- • MPU: System design is complex. Requires MPU + external power management chip + external DDR memory chip + external storage chip + clock chip + various interface expansion chips + complex PCB routing (especially for high-speed memory buses). A minimal system board is usually already a complex circuit board.
4.Performance and power consumption
- • MCU: Lower clock frequency (MHz – several hundred MHz), low power consumption (usually in the mW – several hundred mW range), suitable for battery-powered and real-time control.
- • MPU: Higher clock frequency (GHz), powerful performance, high power consumption (usually in the W to tens of W range), requiring active cooling or good thermal design.
5.Pin count and packaging
- • MCU: Moderate pin count (a few to hundreds of pins), various packaging forms (QFN, LQFP, BGA, etc.), but relatively low pin density.
- • MPU: Very high pin count (hundreds to thousands of pins), almost always uses BGA (Ball Grid Array) packaging to meet the needs of high-speed signals and numerous connections.
Typical Chip Examples (by Architecture)
ARM Architecture
| Type | Chip Example | Features |
|---|---|---|
| MCU | STM32F407 (Cortex-M4) | Built-in 192KB SRAM + 1MB Flash, no MMU |
| MCU | NXP i.MX RT1170 | Cortex-M7, optional MMU but still has built-in RAM/Flash |
| MPU | BCM2711 of Raspberry Pi | Cortex-A72, requires external LPDDR4, includes MMU |
| SoC | Snapdragon 8 Gen 2 | Integrates Cortex-X3/A715 (MPU) + GPU + 5G Modem |
PowerPC Architecture
| Type | Chip Example | Features |
|---|---|---|
| MCU | NXP MPC5744P | e200z4 core, built-in 4MB Flash + 512KB RAM |
| MPU | NXP T2080 | 4-core e6500, requires external DDR3, includes MMU |
| SoC | PS3 Cell Processor | PowerPC core + coprocessor, external XDRAM |
x86 Architecture
| Type | Chip Example | Features |
|---|---|---|
| MCU | Intel Quark D2000 | Pentium instruction set, built-in Flash |
| MPU | Intel Core i7-13700K | Requires external DDR5 + SSD, includes MMU |
| SoC | AMD Ryzen Embedded V1807B | Integrates Zen core + Radeon GPU, requires external DDR4 |
Summary and Key Distinctions
| Feature | CPU | MCU (Microcontroller) | MPU (Microprocessor) |
|---|---|---|---|
| Essence | Core computing unit (core brain) | System on Chip (CPU + memory + storage + peripherals) | Powerful computing core (high-performance CPU core/Cache) |
| On-chip storage | None (only Cache) | Yes (SRAM and Flash/ROM) | No (only Cache, requires external RAM/storage) |
| Peripheral integration | None | Highly integrated (rich and diverse) | Fewer (focus on high-speed interfaces, requires external expansion) |
| System composition | Cannot operate independently | Single chip + few components = minimal system | MPU + complex peripheral circuits = minimal system |
| Performance/Power Consumption | Varies | Low – Medium / Ultra-low – Low | High / High |
| Clock Frequency | Varies | MHz – several hundred MHz | GHz level |
| Applications | All computing cores | Embedded control (appliances, automotive, industrial, IoT) | Complex computing (PCs, smartphones, servers, Linux devices) |
| Operating Systems | OS, bare metal, etc. | Bare metal / RTOS | General OS (Linux, Android, Windows) |
| Key Judgments | Look for core execution unit | Check manual: on-chip Flash/RAM clearly exists | Check manual: requires external DDR memory/large capacity storage |
In summary
- • CPU is the core execution unit.
- • MCU = CPU + memory + storage + peripherals (integrated on a single chip) -> independent embedded control unit.
- • MPU = powerful CPU core + large cache (integrated on a single chip) -> computing core that requires external memory/storage support.
- • Processor is a general term, usually referring to a processing unit that includes a CPU core (CPU or SoC).
When judging, consulting the chip manual to confirm whether it has built-in primary program storage (Flash/ROM) and data storage (RAM) is the most core and reliable method. MCUs clearly tell you how many KB/MB of on-chip Flash and SRAM they have. MPUs will tell you what type of external DDR memory controller they support and what type of external storage interfaces are required.
📌 Key Conclusions
- • MCU: Built-in storage is conclusive evidence (regardless of whether there is an MMU);
- • MPU: Relying on external storage is conclusive evidence (usually has an MMU);
- • SoC: Focus on heterogeneous integration (may contain MCU or MPU cores).
Recommended Reading: Kernels, Instruction Sets, and Architectures (1) Kernels, Instruction Sets, and Architectures (2): Kernels and Peripherals Kernels, Instruction Sets, and Architectures (3): M0 and M3 Kernels