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1. Introduction to the I2C Bus
The I2C bus is a serial, half-duplex bus introduced by Philips in the early 1980s, primarily used for communication between chips over short distances and at low speeds. The I2C bus consists of two bidirectional signal lines: one data line (SDA) for sending and receiving data, and one clock line (SCL) for synchronizing the clocks of the communicating parties. The hardware structure of the I2C bus is simple, which simplifies PCB wiring, reduces system costs, and improves system reliability, leading to its widespread application in various fields.
The I2C bus is a multi-master bus, with devices connected to the I2C bus classified as masters and slaves. The master has the authority to initiate and terminate a communication session, while the slave can only respond to calls. When multiple masters are enabled on the bus simultaneously, I2C also has conflict detection and arbitration features to prevent errors. Each device connected to the I2C bus has a unique address (7 bits), and each device can act as either a master or a slave (but only one master can exist at any given time). Adding or removing devices on the bus does not affect the normal operation of other devices; during communication, the device sending data is referred to as the transmitter, and the device receiving data is referred to as the receiver.
The I2C bus can be online tested through external connections, facilitating system fault diagnosis and debugging, allowing faults to be immediately addressed. Software also aids in standardization and modularization, shortening development time.
The number of devices that can be connected to the I2C bus is limited by the maximum bus capacitance of 400pF.
The serial 8-bit bidirectional data transmission rate can reach up to 100Kbit/s in standard mode, 400Kbit/s in fast mode, and 3.4Mbit/s in high-speed mode.
The bus has extremely low current consumption and strong anti-noise interference capability. Adding bus drivers can increase the bus capacitance by ten times, allowing transmission distances of up to 15m; it is compatible with devices of different voltage levels and has a wide operating temperature range.
2. Communication Process
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The master sends a start signal to enable the bus.
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The master sends a byte of data indicating the slave address and the direction of subsequent byte transmission.
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The addressed slave sends an acknowledgment signal in response to the master.
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The transmitter sends a byte of data.
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The receiver sends an acknowledgment signal in response to the transmitter.
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…….. (Repeat steps 4 and 5)
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After communication is complete, the master sends a stop signal to release the bus.
Steps 4 and 5 use the terms transmitter and receiver, not master and slave, which is determined by the last bit of the first byte indicating whether the master sends to the slave or the slave sends to the master.
In other words, the first byte and the last stop signal are always sent from the master to the slave, but the intermediate communication can vary.
During data transmission, the direction cannot be changed (unless communication is restarted; see the typical I2C timing section later).
3. Addressing Method
The data transmitted on the I2C bus is broad, including both addresses and actual data.
After the master sends the start signal, it must first send a byte of data, where the high 7 bits represent the slave address, and the lowest bit indicates the direction of subsequent byte transmission: ‘0’ indicates the master sends data to the slave, and ‘1’ indicates the slave sends data to the master.
All slaves on the bus compare the 7-bit address with their own address upon receiving this byte of data. If they match, the slave considers itself addressed by the master and then determines whether it will act as a transmitter or receiver based on the 8th bit.
4. Start and Stop Signals
When SCL is high, a transition of SDA from high to low indicates a start signal;
When SCL is high, a transition of SDA from low to high indicates a stop signal;
Both start and stop signals are generated by the master. After the start signal is generated, the bus is considered busy, and after the stop signal is generated, the bus is released and becomes idle.
When idle, both SCL and SDA are high.
There are two scenarios for stopping:
If the master no longer wishes to send, it sends a stop signal;
If the slave no longer wishes to receive and does not acknowledge, the master sends a stop signal to end the communication.
5. Byte Transmission and Acknowledgment
In I2C bus communication, each byte is 8 bits long. During data transmission, the highest bit is sent first, followed by the lower bits. After the transmitter sends a byte of data, the receiver must send a 1-bit acknowledgment to respond to the transmitter, resulting in a total of 9 bits per frame.
Each data transmission in I2C must be 8 bits.
The MSB is fixed, with the high bits sent first, followed by the low bits.
6. Synchronized Data Signals
During data transmission on the I2C bus, when the clock line SCL is low, the transmitter sends one bit of data on the data line. During this time, the signal on the data line is allowed to change. When the clock line SCL is high, the receiver reads one bit of data from the data line. During this time, the signal on the data line must remain stable.
7. Clock Synchronization and Arbitration
(1) Clock Synchronization
Clock synchronization is achieved through the wire-AND of the SCL lines on the I2C bus. If multiple masters generate clocks simultaneously, the SCL line will only show high when all masters send high; otherwise, it will show low.
The wire-AND characteristic is implemented by an open-drain circuit. If the open-drain output INT is controlled to 0 (low), then VGS > 0, and the N-MOS transistor conducts, grounding the output. If the open-drain output INT is controlled to 1 (it cannot directly output high), the N-MOS transistor turns off, so the pin neither outputs high nor low, resulting in a high-impedance state. During normal operation, an external pull-up resistor must be connected. This means that if multiple open-drain mode pins (C1, C2, …) are connected together, only when all pins output high-impedance will the pull-up resistor provide a high level, with the high level voltage being the voltage of the power supply connected to the external pull-up resistor. If any pin outputs low, the line effectively shorts to ground, resulting in the entire line being low, at 0 volts.
(2) Arbitration
Bus arbitration is similar to clock synchronization. When all masters write 1 on SDA, the data on SDA is 1; if any master writes 0, the data on SDA becomes 0.
Each time a master sends a bit of data, it checks the level of SDA against the data it sent while SCL is high. If they do not match, the master knows it has lost arbitration and stops writing to SDA. In other words, if a master consistently finds that the data on the bus matches what it sent, it continues transmission, ensuring that the master that wins arbitration does not lose data.
A master that loses arbitration stops generating clock pulses upon detecting it has lost and can only retransmit when the bus is idle.
The arbitration process may involve multiple bits of sending and checking. In practice, if two masters send data with the same timing and data, both can complete the entire data transmission successfully.
Note: During arbitration among multiple masters, due to the wire-AND characteristic, the one that drives low can force SDA low, meaning it matches itself, so the one that is high (high level 1) will fail arbitration.
8. Typical I2C Timing
(1) Master sends data to slave
(2) Slave sends data to master
(3) Master first sends data to slave, then the slave sends data to the master
Note: S: Start signal, A: Acknowledgment signal, A non indicates no acknowledgment, P: Stop signal,
The shaded part indicates data transmitted from the master to the slave, while the unshaded part indicates data sent from the slave to the master.
If you want to change the transmission direction during data transfer, you do not need to send a P stop signal; the bus will not be released, and you can directly send a start signal again.
How to send a start signal and how to send a stop signal do not need to be concerned about; these are handled by the I2C controller. When we use it, we only need to correctly configure the corresponding registers of the controller.
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Original link:
https://blog.csdn.net/zhangduang_KHKW/article/details/121953275