Detailed Explanation of SPI Protocol (Based on ZhiXin Z20K11X)

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1. Introduction

1. Concept

The SPI (Serial Peripheral Interface) bus protocol is a full-duplex synchronous serial bus communication protocol used for data transmission between integrated circuits. The SPI bus typically consists of one master device and multiple slave devices, each slave device has a separate chip select signal, and it can operate at hundreds of MHz. Generally, SPI requires four lines, but it can also work with three lines.

2. Features

• Synchronous Communication: SPI is a synchronous communication protocol where data transmission is controlled by the clock signal (SCLK) provided by the master device, ensuring synchronized data transmission.
• Full-Duplex Communication: SPI supports full-duplex communication, allowing the master and slave devices to send and receive data simultaneously.
• Multi-Slave Support: A master device can connect to multiple slave devices, selecting a specific slave device for communication through the chip select signal (Chip Select, CS).
• Simple Hardware Connection: Compared to other protocols like I²C, the hardware connection of SPI is relatively simple and does not require complex handshake signals.

3. Advantages and Disadvantages

Advantages:

① High-speed transmission: Due to the absence of complex handshake signals, SPI can achieve high-speed data transmission, almost twice as fast as I²C.

Full-duplex communication: The master and slave devices can send and receive data simultaneously, improving communication efficiency.

② High flexibility: Multiple slave devices can be easily connected, supporting various communication modes, and data transmission is more flexible, allowing transmission of arbitrary-sized words.

③ Simple hardware structure: Slave devices do not require unique addresses (unlike I²C). Slave devices use the master clock and do not need precise clock oscillators/crystals (unlike UART). No transceivers are needed (unlike CAN).

Disadvantages:

① More pin usage: Each slave device requires a chip select signal; if there are multiple slave devices, it will occupy more GPIO pins.

② No flow control and acknowledgment mechanism: The SPI protocol does not have built-in flow control and data acknowledgment mechanisms; these need to be implemented at the application layer.

③ Short transmission distance: Compared to RS-232 and CAN bus, it only supports very short distances.

④ Only one master device is allowed.

4. Application Scenarios

SPI protocol is widely used in scenarios requiring high-speed data transmission and reliability, such as:

① Display driver

② Memory (such as SD cards, Flash memory)

③ Sensor data acquisition

④ Audio codec

⑤ Motor driver

2. Communication Principle

SPI generally consists of four pins (one master and one slave):

SCLK (Serial Clock): Serial clock generated by the master.

MOSI (Master Output Slave Input): Signal output from the master to the slave.

MISO (Master Input Slave Output): Signal input from the slave to the master.

NSS (Slave Selected): Select signal generated by the master, usually active low.

Different chip manufacturers have different naming conventions, and in addition, there are:

SCLK/SCK

MOSI/SOMI/DIN/DI/SDI/SI/SIN

MISO/SIMO/DOUT/SDO/SO/SOUT

NSS/CE/CS/SSEL/PCS

Figure 1 shows the master-slave connection diagram of SPI.

Figure 1

The communication process can be divided into the following steps:

Start Condition (Chip Select): The master selects the slave through the chip select signal (Chip Select) and sends a low-level signal, indicating the start of data transmission.

Transmission Method: Data is transmitted between the master and slave using the two lines MOSI and MISO. The master sends data through MOSI, and the slave receives data through MISO; the timing of data acquisition is determined based on the mode selection.

Clock Signal: The master controls the data transmission rate via the SCLK clock signal, while the slave also receives data at the same clock frequency.

Data Length: The SPI bus does not have a fixed data length limit and can send data blocks of arbitrary length.

End Condition (Chip Deselect): The master cancels the selection of the slave through the chip select signal (Chip Deselect) and ends data transmission.

For example, sending 0x53 as shown in Figure 2: the master pulls down the NSS chip select signal, starts communication, and generates the clock signal, triggering the edge signal on the rising edge. When the master starts sending 0x53 bit by bit on the MOSI signal line (since 0101=0x5, 0011=0x3, so according to the low bit first, it should be 11001010), it receives the data 0X46 bit by bit on the MISO line.

Figure 2

3. Communication Characteristics

SPI is a very flexible communication protocol; we can configure its clock polarity, clock phase, etc.

1. Clock Frequency

The clock frequency of SPI refers to the frequency of the clock signal used for synchronizing data transmission. It determines the speed of data transmission. The configuration of the clock frequency needs to consider the hardware limitations of the master and slave devices and the communication distance.

Configuring the SPI clock frequency mainly involves the following steps:

① Determine the maximum clock frequency of the master: Refer to the technical manual of the master to find the maximum clock frequency supported by the SPI module.

② Determine the maximum clock frequency of the slave: Refer to the technical manual of the slave to find the maximum clock frequency supported by the slave.

③ Choose an appropriate clock frequency: Select an appropriate frequency between the maximum supported frequencies of the master and slave. This frequency should not exceed the maximum supported frequency of either device.

Example: Taking the STM32 microcontroller as an example, the SPI clock frequency is determined by the APB clock and the baud rate prescaler. Below is a configuration example:

① Assume the APB2 clock frequency is 84MHz.

② The baud rate prescaler can be set to 2, 4, 8, 16, 32, 64, 128, or 256. Assume we want to configure the SPI clock frequency to 5.25MHz:

③ SPI clock frequency = APB clock frequency / baud rate prescaler

5.25MHz = 84MHz / 16

④ Therefore, the baud rate prescaler should be set to 16.

2. Clock Polarity (CPOL)

Clock polarity is used to set the level state of the clock when idle,

CPOL is “1” when the clock is high when idle.

CPOL is “0” when the clock is low when idle.

As shown in Figure 3. This directly determines whether the first signal edge is a falling edge or a rising edge, usually CPOL and clock phase (CPHA) are used together.

Figure 3

3. Clock Phase (CPHA)

Clock phase is used to set at which clock edge the data line is sampled,

When CPHA=1, it indicates that the second clock edge samples the data line.

When CPHA=0, it samples the data on the first clock edge.

As shown in Figure 4:

Figure 4

4. Four Modes

Now that we know what phase and polarity are, we can classify SPI into four modes based on their different combinations. The master and slave must operate in the same mode to communicate normally. In practice, “Mode 0” and “Mode 3” are commonly used.

SPI Mode	CPOL	CPHA	Idle CLK Level	Sampling Moment
0	0	0	Low Level	Odd Edge
1	0	1	Low Level	Even Edge
2	1	0	High Level	Odd Edge
3	1	1	High Level	Even Edge

The specific explanations for the four modes are as follows:

Mode0: CPOL=0, CPHA=0: In this case, when idle, SCLK is low, data is sampled on the first edge, which is the transition of SCLK from low to high, so data is sampled on the rising edge (data preparation), and data is sent on the falling edge.

Mode1: CPOL=0, CPHA=1: In this case, when idle, SCLK is low, data is sent on the first edge, which is the transition of SCLK from low to high, so data is sampled on the falling edge, and data is sent on the rising edge.

Mode2: CPOL=1, CPHA=0: In this case, when idle, SCLK is high, data is sampled on the first edge, which is the transition of SCLK from high to low, so data is sampled on the falling edge, and data is sent on the rising edge.

Mode3: CPOL=1, CPHA=1: In this case, when idle, SCLK is high, data is sent on the first edge, which is the transition of SCLK from high to low, so data is sampled on the rising edge, and data is sent on the falling edge.

The specific sampling data is shown in Figure 5:

5. Multi-Master Mode

As mentioned earlier, the SPI bus must have one master and can have multiple slaves. The specific connection methods to the SPI bus are as follows: multiple chip selects and daisy chaining.

(1) Multiple Chip Selects

① Typically, each slave requires a separate CS line.

② To communicate with a specific slave, the corresponding CS signal line can be pulled low, while keeping the states of other CS signal lines high; if two CS signal lines are pulled low simultaneously, it may cause garbled data since both slaves may attempt to transmit data on the same MISO line, resulting in corrupted received data.

(2) Daisy Chain

Daisy chaining is a common connection topology used to serially connect multiple devices, allowing each device to connect with the previous and next devices. Daisy chaining is widely used in many applications, such as serial communication, computer buses, audio devices, and LED light strings.

Characteristics:

• Serial connection: Each device is connected to the next and previous devices through input and output ports.
• Single channel: Data is transmitted through a single channel, sequentially through each device.
• Simplified wiring: Compared to star topology, daisy chaining reduces wiring complexity, as independent connections from each device to the central node are not required.
• Easy expansion: Adding or removing devices is relatively simple, just connect or disconnect the corresponding device.

Advantages:

• Simplified wiring: Reduces the complexity of physical connections.
• Easy expansion: Devices can be easily added or removed.

Disadvantages:

• Accumulated delay: Each device adds data transmission delay.
• Reliability issues: If one device in the chain fails, it may affect the communication of the entire chain.

4. Programming Implementation

Taking the domestic chip ZhiXin Semiconductor’s Z20K118 chip as an example, the example program for using the SPI master to transmit and receive data is provided in the resources:

The hardware block diagram is shown below

The software code is as follows

1. SPI Structure Configuration

2. System Initialization

3. Enable SPI and pull down PCS to select the slave node

4. Send Data

5. Comparison of Three Types of SPI

The three types of SPI usually refer to Standard SPI, Dual SPI, and Queued SPI. The Standard SPI has been introduced, so we will mainly discuss the latter two types of SPI and their differences.

1. Dual SPI

Dual SPI is an enhanced SPI communication mode mainly used to increase data transmission rates. It adds data transmission channels so that more data can be transmitted in each clock cycle.

Dual SPI is only applicable to SPI Flash, not to all SPI peripherals. For SPI Flash, full-duplex is not commonly used, so it extends the use of MOSI and MISO to work in half-duplex mode, doubling the data transmission. In other words, for Dual SPI Flash, a command byte can be sent to enter dual mode, making MOSI SIO0 (serial io 0) and MISO SIO1 (serial io 1), allowing 2 bits of data to be transmitted in one clock cycle, effectively doubling the data transmission.

Features

• Dual-channel data transmission: Uses two data lines to transmit data simultaneously, usually MOSI and MISO transmitting data together.
• Higher transmission rate: Dual SPI can transmit more data than Standard SPI at the same clock frequency.
• Higher hardware requirements: Requires master and slave devices that support Dual SPI mode.

2. Queued SPI

Queued SPI is an advanced SPI communication mode, typically used in scenarios requiring efficient management of multiple SPI transmission transactions. It adds hardware queue functionality on top of Standard SPI, allowing multiple SPI transmission transactions to be pre-configured, and the master can automatically execute these transactions sequentially.

Queued SPI is the abbreviation for Queued SPI, which is based on Dual SPI and adds two I/O lines (SIO2, SIO3) to transmit 4 bits in one clock cycle.

Features

• Hardware queue: Allows pre-configuration of multiple transmission transactions, which are executed automatically by hardware.
• Efficient management: Reduces CPU intervention and improves data transmission efficiency.
• Suitable for complex scenarios: Particularly suitable for applications requiring frequent and complex SPI transmissions, such as memory access.

Dual SPI and Queued SPI are aimed at flash interfaces, modifying full-duplex to half-duplex based on the characteristics of flash operation, thereby increasing communication speed.

3. Differences Among the Three

(1) Standard SPI is general-purpose, while Dual SPI and QSPI are only applicable to flash;

(2) Standard SPI: Standard 4-wire connection, full-duplex, simultaneous sending and receiving;

(3) Dual SPI: Standard 4-wire connection, half-duplex, 2 data lines, bidirectional switching;

(4) QSPI: Standard 4-wire connection, half-duplex, 4 data lines, bidirectional switching.

Feature	Standard SPI	Dual SPI	Queued SPI
Data Channel	Single Channel	Dual Channel	Single or Dual Channel
Data Rate	Regular	Higher	Efficient Management
Hardware Complexity	Simple	Requires Dual SPI supporting devices	Requires QSPI supporting devices
Transmission Rate	Normal	Higher	Highest
Application Scenario	General SPI Communication	High-speed Data Transmission	Complex, Frequent SPI Transmission

The differences in code configuration are illustrated using the STM32F4 HAL library as an example:

① Standard SPI code configuration

② Dual SPI code configuration

When configuring Dual SPI, it is necessary to additionally set the dual-channel mode for the data lines:

③ QSPI code configuration

QSPI configuration is relatively complex and requires configuring queue management and multi-channel modes

Source: CongCong 0606

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Original link:

https://blog.csdn.net/2201_75342985/article/details/139789971