The Neoverse N1 was launched two years ago and has been a great success for Arm and our partners. More and more cloud provider users are seeing incredible performance per watt and per dollar. In terms of 5G and networking, partners are building differentiated solutions that are already powering the next wave of 5G solutions.Neoverse N2 – Arm’s First Armv9 Infrastructure CPUThe Neoverse N2 introduces new features based on the legacy issues of Neoverse N1 and Neoverse V1, drawing from Armv8.4, Armv8.5, Armv8.6, and Armv9. In the following sections, I will focus on some of these features.
Performance: SVE2The Neoverse N2 is our first infrastructure core with Scalable Vector Extension version 2 (SVE2). SVE2 builds on Scalable Vector Extension (SVE) to bring scalable SIMD vector performance and advanced automatic vectorization capabilities to a broader range of software, including ML, DSP, regular expressions, and 5G RAN.For traditional architectures, every time a new vector length is introduced in hardware, the code must be rebuilt and optimized to take advantage of the additional vector bandwidth. Both SVE and SVE2 are vector-length agnostic SIMD instruction sets, allowing users to write and optimize code once, compile it once, and run it on various hardware. SVE/SVE2 automatically adjusts the code to fully utilize the available vector bandwidth. As new technologies enable us to build larger vector machines, code written and compiled using SVE/SVE2 will automatically scale to these larger machines.SVE2’s simpler programming model, along with a new vector length version that is independent of Neon instructions, allows compilers to more easily perform automatic vectorization. This enables programmers to take advantage of vectorization benefits without having to do anything special. While the Neoverse N2 continues to fully support NEON for pre-existing/pre-optimized code, we recommend focusing new development/optimization efforts on SVE2. Because it is vector-length agnostic, SVE2 can greatly extend the lifespan of ROI in software development and investment development.Performance: Microarchitecture UpdatesThe Neoverse N2 brings a 40% IPC improvement over the Neoverse N1 (SPECint2006 est.). It achieves this improvement while maintaining a very similar area/power efficiency to the Neoverse N1 and is a balanced CPU. This performance boost does not come from any one microarchitecture feature, but rather from comprehensive improvements. This improvement is not limited to synthetic benchmarks; we have also seen strong gains in real server workloads.As CPU designers pursue performance improvements, achieving performance without incurring exponentially increased power and area efficiency costs becomes increasingly difficult. In designing the Neoverse N2, we were very focused on maintaining the CPU’s power and area efficiency without compromising performance. To eliminate these conflicting goals, we managed to position the Neoverse N2 at the corner of this curve. For the new microarchitecture features in the N2, our threshold was high; they had to deliver strong power and area ROI. Additionally, we spent significant time optimizing existing structures to enhance performance and efficiency.Relative to Neoverse V1, the Neoverse N2 relies less on pipeline width and depth to achieve its performance. The Neoverse N2 also has more moderate speculation, vector bandwidth, and load/store bandwidth. The Neoverse N2 retains many effective features from the Neoverse V1, including branch prediction algorithms, data prefetch algorithms, and replacement strategies. Additionally, the Neoverse N2 includes the Mop cache introduced in the Neoverse V1, which provides strong performance improvements on small cores that frequently appear in infrastructure workloads. All of this is aimed at maintaining the balance of the core while achieving strong performance improvements on workloads related to cloud-to-edge scenarios.ScalabilityAs the Neoverse N2 is part of our N series, it must be a highly scalable CPU, providing our partners with freedom from cloud to edge space. Partners can build low core count, low frequency, power envelope optimized systems, or take the same N2 core and build monsters with high core counts, high frequencies, and large memory bandwidth for data centers. In such large systems, efficiency profiles enable partners to accommodate more threads per slot. As infrastructure SoCs grow, managing shared resources becomes increasingly important. I would like to introduce some of the new features we have added to further enhance the scalability of these large systems.Memory Partitioning and Monitoring (MPAM)
MPAM restricts process interactions and interference in shared resources and provides a mechanism to track and control access to shared system resources (such as cache and memory bandwidth) at a process granularity. The Neoverse N2 assigns tags to transactions as they leave the CPU. These tags are retained in transactions as they work through system shared resources. This provides a mechanism for intelligent agents along the path to monitor, restrict, or guarantee the amount of resources available to processes. In large systems, MPAM can help alleviate noisy neighbors and help achieve service level agreements (SLA).Completer Busy (CBusy)
CBusy provides a mechanism to automatically adjust CPU traffic requests based on overall system congestion. We are all very familiar with local highway systems, so if congestion occurs, no one can make much progress. CBusy provides a method to regulate CPU in the system to prevent this congestion and related retries, which only complicate the issue. CBusy signals start by limiting speculative transactions, but if congestion is severe enough, it can also limit all transactions. The goal of CBusy is to maintain optimal use of queued resources while limiting congestion. This allows the Neoverse N2 to utilize all available bandwidth in uncongested environments while limiting its usage in congested situations to provide better system-level performance.Power Efficiency and Management with Performance Defined Power Management (PDP)The Neoverse V1 introduced two key mechanisms that aid in power management: Maximum Power Mitigation Mechanism (MPMM) and Scheduling Throttling (DT). These mechanisms allow partners to build systems that maximize performance within power budgets. Both are included in the Neoverse N2.In the Neoverse N2, we have also added a new mechanism called Performance Defined Power Management (PDP). The goal of PDP is to properly adjust the power consumption of workloads, allowing the CPU to dynamically scale its microarchitecture to maximize power efficiency for a given workload. PDP distributes multiple levers across the CPU that can change the width, depth, and speculation of the CPU to match the microarchitecture to the workload being run. PDP not only affects the total power of the cores but also enhances the power efficiency of the cores.SecurityThe importance of security in our infrastructure cannot be overstated, whether discussing cloud servers or 5G base stations; security is a primary factor in any design. The Neoverse N2 provides many new features to help meet this demand.Pointer Authentication (PAC) and Branch Target Identification (BTI)
-
Prevent code reuse attacks aimed at return-oriented programming from jump-oriented programming.
-
Provide mechanisms to minimize the gadgets available for exploitation by malicious actors. On GLIBC, enabling PAC and BTI can reduce the number of available gadgets by over 97%, with only a 1% to -2% loss in code size.
Memory Tagging Extension (MTE)
-
Memory safety issues account for 70% or more of security vulnerabilities.
-
MTE provides a mechanism to detect memory safety violations. MTE helps detect potential vulnerabilities before deployment by improving the efficiency of testing and fuzzing. MTE also aids in large-scale detection of vulnerabilities after deployment.
-
Easy-to-deploy memory safety violation detection and mitigation measures can prevent a large number of security vulnerabilities from being exploited.
Secure EL2Today, the world of security is all or nothing. If an application is trusted and placed in a secure world, it is difficult to restrict its access to trusted areas. However, as we enter a world with many different applications provided by different vendors, many of which live in secure worlds, it becomes increasingly important to isolate these applications from each other. Secure EL2 extensions increase support for virtualization in the secure world. This will bring the functionality available for virtualization in the non-secure state into the secure state and enable secure partition managers. Secure partition managers enable secure space partitioning, providing the necessary secure access permissions for partitions while isolating them from each other.Neoverse N2’s Arm POP IPAs part of our N2 platform, we have also developed optimal physical implementation solutions under the Neoverse POP IP umbrella to accelerate time to market. Neoverse N2 POP IP is available in cutting-edge 5nm processes, with many processes transitioning. Comparing the N1 on the left with the N2 on the right shows a 40% IPC improvement. Additionally, with the transition to 5nm, we have the potential to increase frequency by 10% while keeping power and area roughly the same. If Neoverse N1 PPA is very suitable for your workload and 7nm power range, then 5nm Neoverse N2 is ideal.
Neoverse N2 Reference DesignIn addition to our Neoverse cores, we also provide critical resources for partners to enable rapid start designs. We will provide a Neoverse N2 reference design along with the CPU. This reference design is aimed at 5G, networking, SmartNIC, and hyperscale.
-
Enabling partners to guide designs.
-
Providing architectural guidance and best practices.
-
Enabling left-shift software development.
Included in the reference design:
-
PPA and benchmark results to help you determine scale.
-
Technical guidance for building comparable systems.
-
Fixed virtual platforms for software development.
-
Reference software stack.
Our goal with these reference designs is to enable partners to launch operating systems on day one. For more information about the reference design, please visit the Neoverse reference design page.
ConclusionThe Neoverse N2 platform significantly raises the standard for performance efficiency from cloud to edge. It builds on the incredible traction established by the Arm Neoverse ecosystem alongside Neoverse N1 while bringing key upgrades in performance, efficiency, and security. We expect our partners’ Neoverse N2 silicon to be available for sampling by the end of 2021. We can’t wait for customers to experience the additional benefits that Neoverse N2 will bring to cloud-to-edge solutions.
Original Author: Mohit Taneja
END
关于安芯教育
安芯教育是聚焦AIoT（人工智能+物联网）的创新教育平台，提供从中小学到高等院校的贯通式AIoT教育解决方案。
安芯教育依托Arm技术，开发了ASC（Arm智能互联）课程及人才培养体系。已广泛应用于高等院校产学研合作及中小学STEM教育，致力于为学校和企业培养适应时代需求的智能互联领域人才。