Helium technology, which is the M-profile Vector Extension (MVE) of Arm, is a crucial part of the ARM v8.1M architecture.
Currently, the cores under the ARM v8.1M architecture include Cortex®-M52, Cortex®-M55, and Cortex®-M85. For example, last year Renesas released the Cortex-M85 core RA8 series microcontroller.
The following table, Arm Cortex-M Processor Comparison Table, details the differences between Arm®v6 and Arm®v8.1M cores. It is easy to see that the Cortex®-M85 is currently the most powerful Arm® Cortex®-M core MCU.
Copy the link to your browser to access the original table:
https://armkeil.blob.core.windows.net/developer/Files/pdf/product-brief/arm-cortex-m-processor-comparison-table.pdf
Arm v8.1-M architecture is an extension of Arm v8-M architecture. In addition to the new vector instruction set architecture (Helium), there are several other new features:
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Additional instruction set for enhanced loops and branches (Low Overhead Branch Extension).
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Support for half-precision floating-point instructions.
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Enhanced debugging features, including Performance Monitoring Unit (PMU) and debugging features for signal processing application development.
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TrustZone management enhancement instruction set for FPU.
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Non-privileged debugging extension.
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The Memory Protection Unit (MPU) provides a new memory attribute, “Privileged eXecute Never (PXN)”. This allows the prevention of executing arbitrary code when the CPU is in privileged mode, which may have been written to user space. This is an important security feature.
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Reliability, Availability, and Serviceability (RAS) extensions.
The introduction of Helium aims to achieve more efficient DSP and machine learning operations on Cortex®-M core MCUs. It shares many similarities with Neon in Cortex®-A core MPUs. Both Neon and Helium use registers in the FPU as vector registers. Both use 128-bit vectors, and many vector processing instructions are common to both architectures. However, Helium is a completely new design that achieves efficient signal processing performance in small processors. It provides many new architectural features for embedded use cases, as it is optimized for area (cost) and power consumption, bringing Neon-like capabilities (Cortex-A’s SIMDnote instructions) to the M-Profile architecture. Helium is optimized to effectively utilize all available hardware in smaller Cortex-M cores. The following table provides detailed comparisons between Helium and Neon.
Helium vs Neon Comparison Table
Note: SIMD (Single Instruction Multiple Data) refers to the ability to execute the same operation on multiple data items simultaneously across multiple processing units in the hardware, meaning that the CPU can perform parallel computations while only one instruction is being executed. This is data-level parallelism.
Currently, many systems combine Cortex-M processors with dedicated programmable DSP processors. Helium allows such systems to be implemented with just one processor. The advantages of this approach include:
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From a software development perspective, it allows the use of a single toolchain instead of separate compilers and debuggers for CPU and DSP. This means programmers only need to be familiar with one architecture.
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Eliminates the need for inter-processor communication, which can be crucial as debugging different software on two runtime processors with real-time interaction is both difficult and time-consuming.
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The Cortex-M series CPU is easier to program compared to dedicated DSPs.
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At the hardware design level, using one processor (instead of two) can simplify the system, thus reducing chip area and cost, and shortening development cycles.
Before detailing Helium, let’s discuss the concepts of scalars and vectors.
Perspective in Mathematics and Physics
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A scalar is a quantity that has only magnitude
– For example, pure numbers, mass, rate, temperature, volume, etc.
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A vector is a quantity that has both magnitude and direction
– For example, velocity, acceleration, displacement, gravity, friction, etc.
Perspective in Computer Science
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A scalar (processor) processes one data element at a time.
– Typically used for general computational tasks, such as word processing and spreadsheets.
– Low power consumption, inexpensive.
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A vector (processor) performs the same operation on multiple sets of data (usually two data per set) in batches, obtaining a batch of results. For example, adding 100 addends to 100 augends simultaneously to get 100 sums.
– Particularly useful for tasks that require parallel processing of large amounts of data, such as image, video, and audio data processing.
– Can also be used for scientific computing, accelerating complex algorithm processing.
– Higher power consumption, slightly higher cost.
Helium Registers, Data Types, and Channels
Helium registers are 128 bits wide, with a total of 8 Helium registers that cannot be modified. They are used in conjunction with the floating-point unit (FPU). In the FPU, S0~S31 are used to access 32 single-precision (32-bit) registers, and the same hardware registers can also be viewed as 16 double-precision (64-bit) registers D0~D15. For example, D0 shares the same 64-bit hardware register with S0, S1. In the Helium architecture, Helium uses 8 vector registers Q0~Q7. This means that Helium register Q0 shares the same physical registers with S0~S3, D0~D1 floating-point registers, Q1 shares the same physical registers with S4~S7, D2~D3 floating-point registers, and so on. Because Helium registers reuse scalar FPU registers, there is no need for additional resources to save and restore these registers when exceptions occur (which also does not affect interrupt latency).
Each Helium register can be divided into 8-bit, 16-bit, and 32-bit wide channels. Each channel can be treated by an instruction as:
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Integer values (8/16/32 bits wide)
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Fixed-point saturated values (Q7/Q15/Q31)
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Floating-point values (half-precision FP16/single-precision FP32)
The following diagram is an example of adding vector registers. Both Helium register q5 and q0 contain 8 elements of int16 (8 channels), and the result of their addition is stored in q0.
Helium allows each channel in the vector to execute conditionally, known as channel prediction. The Vector Prediction Status and Control Register (VPR) stores the condition values for each channel. Certain vector instructions (such as vector comparison VCMP) can modify the condition values in the VPR. Once these condition values are set, the subsequent VPT (Vector Conditional Prediction) instruction can implement conditional execution based on each channel in the vector prediction.
Renesas Electronics launched the powerful RA8 series MCUs at the end of October 2023, featuring a groundbreaking 3000 CoreMark, meeting the requirements for complete determinism, low latency, and real-time operation needed by customer applications. The RA8 series MCUs are also the industry’s first products to adopt the Arm® Cortex®-M85 processor, providing outstanding 6.39 CoreMark/MHz performance—this performance level will enable system designers to replace commonly used microprocessors (MPUs) in applications with RA MCUs. The new product line is part of the well-received RA product family based on Arm Cortex-M processors. Additionally, existing designs built for other RA products can be easily ported to the new RA8 MCUs.
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