Today, semiconductor companies face severe challenges related to shrinking technology nodes, expanding design scales, and broadening system scales (known as the “three major scaling challenges”). These challenges have a wide-ranging impact on design development, manufacturing, and functional operations, all of which affect the company’s operating profits. At the same time, the complexity of large System … Read more
In the wave of rapid expansion of RISC-V, SoC design is becoming increasingly complex, and the debugging phase faces unprecedented challenges. Accurately reproducing hidden bugs, quickly analyzing system bottlenecks, and ensuring the correctness of custom logic have become key to the maturity of the RISC-V ecosystem. At the 2025 RISC-V China Summit, Siemens EDA Customer … Read more
[Image][Image][Image] On June 2nd, Chip Ranking reported that the success rate of chip tape-outs has dropped to a historical low! According to Siemens EDA data, the success rate of first-time design finalization (Tape-out) has fallen to 14%, a significant decrease from 24% two years ago. Eight out of ten companies experienced failures in their first … Read more