DNL

Testing Multi-Stage DACs: A Practical Approach

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Testing Multi-Stage DACs: A Practical Approach

“When testing the Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) of multi-stage DACs, it is usually unnecessary to perform a full test on all codes. Instead, validation can be achieved by carefully selecting a subset of key codes.” For example: a 16-bit 3-stage DAC, which internally contains 3 sub-DACs (7-bit, 5-bit, 4-bit), requires scanning all … Read more

High-Level Capacitor Calibration for ADCs

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High-Level Capacitor Calibration for ADCs

“A 12-bit 104-MS/s SAR ADC in 28nm CMOS for Digitally-Assisted Wireless Transmitters”The calibration method introduced here utilizes low-level capacitors to calibrate high-level capacitors, as the absolute mismatch of high-level capacitors is greater, which in turn has a larger impact on DNL and INL. Calibrating high-level capacitors can effectively improve the dynamic range of the ADC.As … Read more