Essential FPGA Written Exam Questions
1. Implement the detection of the 10010 code using a state machine, for example, x=1001001000 z=0000100100 (output) Examines state machines (similar questions exist, need to fully understand) Verilog module check(rst_i,clk_i,data_i,data_o); input rst_i,clk_i; input data_i; output data_o; reg[3:0] current_state,next_state; parameter[3:0] idle="0000", state1="0001", state2="0010", state3="0100", state4="1000"; always@(posedge clk_i or negedge rst_i)if (!rst_i) current_state <= idle; else current_state … Read more