Understanding FPGA: A Comprehensive Guide

Section 1: What is FPGA?

FPGA stands for Field-Programmable Gate Array, which is a type of integrated circuit that can be programmed in the field. It is a product that has further developed from programmable devices such as PAL, GAL, and CPLD. FPGA appears as a semi-custom circuit in the field of Application-Specific Integrated Circuit (ASIC), solving the shortcomings of custom circuits and overcoming the limitation of the number of gates in original programmable devices. In simple terms, FPGA is a chip that can change its internal structure through programming.

FPGA Function Implementation: To implement functions, hardware description languages must be programmed, compiled, synthesized, and routed using EDA tools to create a file that can be burned into the FPGA device, ultimately changing the internal connections of the FPGA to complete the desired functionality.

FPGA Performance Comparison: Compared to integrated circuit chips like microcontrollers and CPUs, FPGA has higher efficiency and lower power consumption. However, its ease of development is far inferior to that of microcontrollers and CPUs. In the field of digital chip design, although FPGA has a shorter development cycle and lower difficulty compared to ASIC, it has issues such as high cost, poor performance, and lower resource utilization compared to ASIC, making it unable to truly replace ASIC.

Section 2: Basic Structure of FPGA

The programmable nature of FPGA determines that its structure for implementing digital logic cannot be completed with fixed logic gate circuits like dedicated ASIC, but can only adopt a structure that can be reconfigured repeatedly. The Look-Up Table (LUT) meets this requirement well, and the current mainstream FPGA chips are still based on SRAM technology with a LUT structure.

FPGA Chip Parameter Indicators: These include the number of programmable logic modules, the number of fixed-function logic modules (such as multipliers), and the size of memory resources (such as embedded RAM).

At the lowest level of configurable logic modules (such as logic units on the chip), there are two basic components: flip-flops and Look-Up Tables (LUT). The combination of flip-flops and LUTs is an important basis for distinguishing between different FPGA families, and the structure of LUTs themselves may also vary (4-input, 6-input, or others).

The Look-Up Table (LUT) is essentially a RAM. Currently, most FPGAs use 4-input LUTs, where each LUT can be seen as a RAM with 4 address lines.

When a user designs a logic circuit through a schematic or hardware description language in an EDA tool, the FPGA development software automatically calculates all possible results of the logic circuit and writes the truth table (i.e., results) into the RAM in advance. Thus, each time a signal is input for logical operations, it is equivalent to inputting an address for LUT operations, retrieving the corresponding result from RAM through the address, and finally outputting it. For example, to implement the logic of Y=A&B&C, if it were in a dedicated ASIC, the logic gates would have been predetermined, and the output value Y would be the result of two logical AND operations, with the basic implementation structure shown below:

The basic structure of Y=A&B&C implemented using FPGA:

Section 3: More Complex FPGA Architectures

With advancements in technology and process nodes, the capacity and performance of FPGA continue to improve, while its power consumption is also being optimized and reduced. Before 2006, 4-input LUTs were widely used, and in some high-end devices, six-input, eight-input, or more input ports may be used for LUTs. A multi-input LUT can be decomposed into smaller input LUTs, meaning it can split into many smaller functions. For example, an eight-input LUT can be divided into two four-input LUTs or one three-input and one five-input LUT. In actual high-end devices, this programmable structure can describe the equivalent of millions (sometimes even tens of millions) of primitive logic gates.

Internally, FPGA utilizes its programmability to construct a counter logic, distinguishing between “soft cores” and “hard cores.”

Soft Core (Soft Function): The functions used in constructing counter logic can be referred to as soft functions.

Hard Core (Hard Function): If a function is implemented directly using the chip, it utilizes the chip’s internal hard functions.

Soft and hard cores complement each other; the advantage of soft cores lies in their ability to utilize chip resources based on programming design to achieve any required function (note that this refers to digital functions, excluding analog functions). In contrast, hard cores are fixed-function devices, hence their advantages include high resource utilization and low power consumption, occupying smaller silicon area, and providing higher performance. The most significant difference is that hard cores can be used to implement analog functions compared to soft cores, such as the frequency-doubling function of a phase-locked loop, which needs to be realized in an analog circuit, thus this part is implemented with hardware inside the FPGA.

Section 4: FPGA with Embedded Processors

One of the things achieved using the programmable structure of FPGA is the use of some of the digital logic resources to create one or more soft processor cores; of course, different scales of processors can also be implemented.

This chip is a new SoC (System on Chip) FPGA, completely implemented in hard core mode with a dual ARM Cortex-A9 microcontroller subsystem (running at clock speeds up to 1GHz, including floating point engine, on-chip cache, counters, timers, etc.) as well as a wide variety of hard core interface functions (SPI, I2C, CAN, etc.), and a hard core dynamic memory controller, all of which enhance performance using a significant amount of traditional programmable structures and a large number of general-purpose input/output (GPIO) pins.

Section 5: Data Storage and Configuration Methods

Inside FPGA, there are storage unit RAM blocks, where data is stored in RAM and used to set the working state. To operate FPGA, programming of the internal RAM is required. If there is a large amount of data interaction externally, peripherals must be added for temporary data storage, such as SDRAM or DDR3 memory; data temporarily stored in peripherals will ultimately also be stored and processed through the internal RAM of FPGA. After the program design is completed in the EDA tool, the software program needs to be burned into the internal FPGA. Different configuration modes provide different programming methods for the FPGA.

Several commonly used configuration modes:

1. Parallel Mode: Configuring FPGA through parallel PROM (Programmable Read-Only Memory) or Flash (Macromedia Flash, a multimedia software platform);
2. Master-Slave Mode: Using one PROM to configure multiple FPGAs;
3. Serial Mode: Configuring FPGA with serial PROM;
4. Peripheral Mode: Using FPGA as a peripheral to a microprocessor, programmed by the microprocessor.

Currently, mainstream FPGAs are based on SRAM (Static Random-Access Memory) technology, and most FPGA development boards use serial configuration mode. Since SRAM loses its internal data upon power loss, it is common to connect an external memory that can retain data during power loss to save the program. Thus, when powered on, the FPGA reads data from the external memory into the internal RAM to complete configuration, entering working state after programming. Upon power loss, the data stored in the internal SRAM of FPGA is lost, and the logic resets. This configuration method allows FPGA to be reused without needing repetitive manual configurations. After completing an active configuration, every time it powers on, it will automatically realize the internal programming of FPGA.

There are relatively many job opportunities for FPGA in major chip manufacturing companies, while embedded consumer companies have very few positions. I know a classmate who started learning FPGA from university; we used FPGA to complete our project in the electrical competition that year, and he has continued to work in FPGA development since then.

I hope those who are interested in FPGA will persist in their preferred direction, as there will surely be shining moments in the future.

Source: https://blog.csdn.net/Royalic/article/details/120979987