Understanding ZYNQ: The Integration of ARM and FPGA

The highlight of the Zynq series is that it contains a complete ARM processing subsystem (PS), each Zynq series processor includes a Cortex-A9 processor, the entire processor is built around the processor, and the memory controller and a large number of peripherals are integrated into the processor subsystem, allowing the Cortex-A9 core to operate completely independently of the programmable logic units in the Zynq-7000. This means that if the programmable logic unit part (PL) is not temporarily used, the ARM processor subsystem can still operate independently, which is fundamentally different from previous FPGAs, as it is processor-centric.Zynq consists of two major functional blocks, the PS part and the PL part, simply put, it is the ARM SOC part and the FPGA part. The PS integrates two ARM Cortex™-A9 processors, AMBA® interconnect, internal memory, external memory interface, and peripherals. These peripherals mainly include USB bus interfaces, Ethernet interfaces, SD/SDIO interfaces, I2C bus interfaces, CAN bus interfaces, UART interfaces, GPIO etc. The following diagram is the overall block diagram of the ZYNQ chip.

Internally, the ZYNQ chip implements the AXI bus protocol in hardware, including 9 physical interfaces, namely AXI-GP0~AXI-GP3, AXI-HP0~AXI-HP3, AXI-ACP interfaces.

The AXI_ACP interface: An interface defined under the ARM multicore architecture, translated into Chinese as the accelerator consistency port, used to manage DMA and other non-cacheable AXI peripherals, with the PS end being the Slave interface.

The AXI_HP interface: A high-performance/bandwidth AXI3.0 standard interface, a total of four, with the PL module acting as the master device connected. It is mainly used for PL to access the memory on the PS (DDR and On-Chip RAM).

The AXI_GP interface: A general AXI interface, a total of four, including two 32 bit master device interfaces and two 32 bit slave device interfaces.

The ZYNQ is the first product to tightly integrate high-performance ARM Cortex-A9 series processors with high-performance FPGA on a single chip. To achieve high-speed communication and data interaction between the ARM processor and the FPGA, leveraging the performance advantages of both, it is necessary to design an efficient interconnection path between the high-performance processor and the FPGA . Therefore, how to design an efficient PL and PS data interaction path is the top priority in ZYNQ chip design and one of the key factors for product design success or failure. In fact, in specific designs, we often do not need to do too much work in this connection area; after we add the IP core, the system will automatically use the AXI interface to connect our IP core to the processor, we just need to make a little supplement. The AXI is a part of the AMBA (Advanced Microcontroller Bus Architecture) proposed by ARM, which is a high-performance, high-bandwidth, low-latency on-chip bus, also used to replace the previous AHB and APB buses. The first version of the AXI (AXI3) was included in the AMBA3.0 released in 2003, and the second version of AXI (AXI4) was included in the AMBA 4.0 released in 2010.

In ZYNQ , three types of buses are supported: AXI-Lite, AXI4 and AXI-Stream :

AXI4-Lite: It has lightweight and simple structure characteristics, suitable for small batch data and simple control scenarios. It does not support bulk transfer, and can only read or write one word at a time (32bit). It is mainly used to access some low-speed peripherals and control peripherals.

AXI4: The interface is similar to AXI-Lite but adds a feature for bulk transfer, allowing for continuous read and write to a block of addresses at once. This means it has data read and write burst functionality.

The above two types both adopt memory-mapped control mode, that is, the ARM compiles the user-defined IP into a certain address for access, when reading and writing, it is like reading and writing its own on-chip RAM, programming is also very convenient, and the development difficulty is relatively low. The price is that it occupies too many resources, requiring additional read address lines, write address lines, read data lines, write data lines, write response lines and other signal lines.

AXI4-Stream: This is a continuous flow interface, which does not require address lines (similar to FIFO, just read or write continuously). For this type of IP, ARM cannot control it through the above memory-mapped method (FIFO has no concept of address), and must have a conversion device, such as the AXI-DMA module to implement the conversion from memory-mapped to stream interface.AXI-Stream is applicable in many scenarios: video stream processing; communication protocol conversion; digital signal processing; wireless communication, etc. Its essence is to construct a data path for numerical streams from the source (such as ARM memory, DMA, wireless receiving front end, etc.) to the destination (such as HDMI displays, high-speed AD audio outputs, etc.), creating a continuous data stream. This interface is suitable for real-time signal processing.

In the above diagram, it can be seen that the interaction between PS and PL can also be done through DMA and EMIO. In fact, DMA is used for PS and PL interaction from the HP port, and when we do not want to waste the AXI bus, we can use EMIO for PS and PL interaction. Understanding MIO, EMIO, and GPIO can be visually understood through the following three LED operations: (1) PS lights up the PS side LED through MIO; (2) PS lights up the PL side LED through EMIO; (3) PS lights up the PL side LED through AXI.

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