(Source: hackday)The Instruction Set Architecture (ISA) defines the software interface through which a Central Processing Unit (CPU) can be controlled. Unlike early computer systems that lacked a defined standard ISA, the advantages of compatibility and portability with a standard ISA have become evident over time. However, the best part of standards is that there are many of them, leading each CPU manufacturer to establish its own standard.Throughout the 1980s and 1990s, as the computer industry consolidated around several major ISAs for various types of applications, the number of mainstream ISAs sharply declined. Intel’s x86 triumphed on desktops and small servers, while ARM emerged victorious in low-power and portable devices, and for Big Iron, IBM’s Power ISA was always a choice. Since our last report on the ISA battle in 2019, many changes have occurred, including Apple’s transition of its desktop systems from x86 to ARM via Apple Silicon, and finally, MIPS has seen a resurgence in the form of LoongArch.Meanwhile, in the previously mentioned article on the ISA battle, RISC-V was mentioned six years ago, but this ISA does not seem to have generated the buzz that some expected. This raises questions about the future development of RISC-V and other ISAs, as well as the significance of having different ISAs in terms of CPU performance and microarchitecture.RISC is EverywhereUnlike the past when CPU microarchitectures were still evolving, today they seem to converge around a similar set of features, including out-of-order execution, prefetching, superscalar parallelism, speculative execution, branch prediction, and multi-core designs. Nowadays, most performance gains are achieved by addressing specific bottlenecks and optimizing for particular use cases, leading to features such as Simultaneous Multithreading (SMT) and various pipeline and instruction decoder designs.Today’s CPUs are almost all based on what was once called RISC (Reduced Instruction Set Computer) architecture, featuring a relatively small number of highly optimized instructions. By employing techniques like register renaming, CPUs can handle multiple threads executing simultaneously, which is completely invisible to the software side communicating with the ISA. For software, there is only one register file, and unless certain situations arise, such as issues with speculative execution, each executing thread is only aware of its own context and nothing else.So, if CPU microarchitectures have essentially merged at this point, what difference does the ISA make?The Scrutiny of Instruction SetsIn the ISA battle, the current debate mainly revolves around the pros and cons of delay slots and compressed instructions, setting status flags versus checking branch results, and other topics. It is difficult to compare ISAs on a like-for-like basis, as the underlying microarchitecture of commercial ARMv8 CPUs differs from similar x86_64 or RV64I or RV64IMAC CPUs. The highly modular nature of RISC-V also adds significant complexity.If we look at the current use of RISC-V in commercial environments, it is primarily employed as simple embedded controllers, where this modularity is an advantage, and compatibility with countless other possible RISC-V extensions is not an issue. Here, using RISC-V has a clear advantage over proprietary internal ISAs, as outsourcing to an open standard project can save costs. However, this is also one of the main weaknesses of this ISA, as the lack of a fixed ISA like ARMv8 and x86_64 makes supporting tasks like the Linux kernel much more complex than it should be.Due to the growing complexity of support, Google has withdrawn its initial support for RISC-V from Android. Since each RISC-V-based CPU only needs to support the basic integer instruction set, while many features like integer multiplication (M), atomic (A), and bit manipulation (B) are optional, all software targeting RISC-V must explicitly test for the presence of required instructions and features, or fallback solutions will be used.When discussing the lack of integer overflow traps and carry instructions in RISC-V, emotions can run high. As for whether compressed instructions are a good idea, the ARMv8 camp argues that they are unnecessary, while the RISC-V camp is eager to defend them, and x86_64 still happily uses double instruction lengths, thanks to its CISC tradition, which can make x86_64 either twice as good or twice as bad compared to RISC-V, depending on whom you ask.Meanwhile, an engineer with extensive experience in ARM recently wrote a lengthy paper discussing the pros and cons of these three ISAs. Their conclusion was that RISC-V is “minimalism taken to the extreme,” with instruction overlap, no conditional codes or flags, but rather requiring comparison and branch instructions. The latter point leads to many compromises, which is also one of the main reasons many believe RISC-V has issues.In summary, compared to the established domains of other ISAs, RISC-V does not have a clear advantage, but its strengths seem to lie primarily in its extreme modularity and lack of licensing requirements, which is seen as a compelling argument that should not prevent people from enjoying a good debate from time to time.A Chinese PerspectiveWhile all regions outside of China have largely consolidated around the aforementioned three ISAs, there are always exceptions. Unlike Russia’s ill-fated Elbrus architecture with its super-large instruction set, China’s efforts in CPUs have yielded more results. Starting with the Loongson CPU, China’s self-developed microprocessor architecture has begun to take shape.Initially, these were CPUs compatible with MIPS. However, starting with the 3A5000 in 2021, Chinese CPUs began to adopt the new LoongArch ISA. In the Linux kernel documentation regarding this ISA, it is described as “somewhat like MIPS or RISC-V,” with three variants ranging from a streamlined 32-bit version (LA32R) and standard 32-bit (LA32S) to a 64-bit version (LA64). The current LS3A6000 CPU features 16 cores supporting SMT. In reviews, these chips have been shown to rapidly catch up with modern x86_64 CPUs, including in terms of overclocking.Of course, since these are hardware launched only in China, very few Western reviewers have conducted independent tests on the LS3A6000 or its upcoming successor, the LS3A7000.In addition to LoongArch, other Chinese companies are also using RISC-V in their microprocessors, such as the AI-focused company SpacemiT, which also produces more general-purpose processors. This includes the K1 octa-core CPU used in MuseBook laptops. Like all commercially available RISC-V-based cores today, this processor is not fast, and even the SiFive Premier P550 SoC has been thoroughly outperformed by the already quite outdated ARM-based SoC of the Raspberry Pi 4.Considering all this, it is not surprising that the ISA landscape outside of embedded systems in China is primarily characterized by LoongArch, a large amount of ARM, some x86_64, and a small amount of RISC-V.It’s All About IPBy comparing Apple Silicon with other ARMv8-based CPUs, the distinction between ISA and microarchitecture becomes clear. While they all support the same version of the ARMv8 ISA, the magic lies in the intellectual property (IP) blocks integrated into the chip. These include memory controllers, PCIe SerDes blocks, integrated graphics (iGPU), as well as encryption and security features. Unless you are Apple or Intel with your own GPU solutions, you will get an iGPU block along with licenses for other IP blocks from IP vendors.The advantage of these IP modules is the ability to use existing features with known performance characteristics, but they also represent a significant portion of the cost of microprocessor design. If you are like Apple or Qualcomm and repeatedly reuse the same modules, then developing such features from scratch can recoup costs. For a startup hardware company, this is one of the largest investments, which is why they tend to license fully manufacturable designs from Arm.The actual licensing costs of an ISA are essentially a rounding error, while the ability to leverage existing software and tools is the main driving factor. This is why a new ISA like LoongArch is likely to pose a real challenge to existing ISAs in the long run, as it has the opportunity to grow in a very large market with guaranteed demand.Multiple ChoicesAt the same time, the Power ISA is also available for anyone to use without licensing fees; the only major requirement is compliance with the Power ISA. The OpenPOWER Foundation is now also part of the Linux Foundation, with a series of IBM Power cores that are open source. This includes the A2O core based on the A2I core that powered the Xbox 360 and PlayStation 3 Cell processor, as well as the Microwatt reference design based on the newer Power ISA 3.0.Regardless of your preference, whether you are working on a hobby or a commercial project, the ISA landscape seems to offer a lot of diversity to choose from. While it is natural to have favorites and enjoy them, each ISA has its merits. Whether it is a better teaching tool, more suitable for highly customized embedded designs, or simply because it can run decades-old software with ease, they all have their place.