Understanding the Interrupt System in STM32

In embedded learning, the STM32 series chips are particularly favored due to their many excellent features, such as the STM32 MCU integrating a wealth of peripherals, including communication interfaces (like UART, SPI, I2C, CAN, etc.), analog and digital interfaces, timers, and interrupt controllers. Today, Little Science introduces the interrupt system of STM32.

In STM32 microcontrollers, the interrupt system is an important mechanism for handling external events and priorities. It allows the microcontroller to respond promptly to specific events while executing the main program. The following are the basic concepts of the STM32 interrupt system:

Interrupt vector table: The interrupt vector table is a table that stores the addresses of interrupt handlers. Each interrupt has a specific vector, and when an interrupt occurs, the microcontroller jumps to the corresponding interrupt handler address based on the interrupt vector table.

Interrupt request: Also known as interrupt source or interrupt event, refers to the signal sent by external devices or internal modules to notify the microcontroller that a specific event has occurred, such as a button press or timer overflow.

Interrupt controller: The interrupt controller is responsible for managing interrupt requests and allocating priorities. STM32 microcontrollers typically have multiple interrupt controller modules, such as the NVIC.

Interrupt priority: Each interrupt has a priority used to determine the execution order of interrupt handlers. Higher-priority interrupts can interrupt lower-priority interrupts or the main program being executed.

Interrupt handler: Also known as interrupt service function, is a piece of code used to handle specific interrupts. When an interrupt occurs, the microcontroller jumps to the corresponding interrupt handler to execute related operations, and after completion, returns to the main program.

Interrupt enable: By setting the corresponding interrupt enable bits, specific interrupts can be enabled or disabled. Once an interrupt is disabled, even if an interrupt request occurs, the microcontroller will not respond.

Interrupt flag: The interrupt flag is used to indicate whether a specific interrupt has occurred. After handling the interrupt, the corresponding interrupt flag needs to be cleared to allow the same interrupt to be triggered again.

When using STM32, you can manage and handle various interrupt requests by configuring the interrupt vector table, interrupt priorities, and enabling interrupts. The interrupt system allows the microcontroller to respond promptly to external events, enhancing the system’s real-time performance and concurrent processing capability.

Interrupts can process burst events in a timely manner, achieving program parallelization and thereby improving CPU efficiency. Interrupts are significant in computer systems, and here are some important meanings of interrupts:

1. Real-time response: Interrupts enable the processor to respond promptly to external or urgent events. Through the interrupt mechanism, the processor can immediately halt the current task and process the interrupt request, ensuring real-time response to important events.

2. Asynchronous processing: The interrupt mechanism allows the processor to handle interrupt events asynchronously without relying on the execution of the main program. This enables the processor to handle multiple concurrent interrupt events while executing the main program, improving the system’s concurrent processing capability.

3. Resource sharing: The interrupt mechanism allows multiple devices or modules to share the processor’s resources. Different devices or modules can issue interrupt requests through the interrupt mechanism, and the processor processes these interrupts based on priority and configuration, achieving reasonable sharing and utilization of resources.

4. Reduced power consumption: In some cases, the processor can enter a low-power mode. By configuring interrupt wake-ups, the processor can wake up only when specific interrupt events occur while in standby or sleep mode, thereby reducing system power consumption. Priority management: The interrupt mechanism allows for priority management of different interrupt requests. By setting interrupt priorities, the processor can ensure that high-priority interrupts are processed in a timely manner, thereby enhancing the system’s real-time performance and responsiveness.

5. System reliability: The interrupt mechanism helps improve the reliability and fault tolerance of the system. Through reasonable design of interrupt handlers and error handling mechanisms, timely responses and appropriate measures can be taken in the event of exceptions or errors, ensuring system stability and reliability.

In summary, the interrupt mechanism plays a crucial role in computer systems, enhancing the system’s real-time performance, concurrent processing capability, resource sharing ability, and providing support for system reliability and maintainability.

[Processing Steps]

Figure 2 Interrupt Flowchart

[Entering Interrupt]

The processor automatically saves the context to the stack {PC, xPSR, R0-R3, R12, LR}. Once the stack operation is complete, the ISR can begin execution.

[Exiting Interrupt]

The context before the interrupt is automatically restored from the stack; once the stack operation is complete, execution of the interrupted instruction continues; the stack operation can also be interrupted, allowing for a new interrupt to be responded to without saving the context.

R0 – R12

R13 Stack Pointer SP: points to the top address of the stack

R14 Link Register LR: stores the return address

R15 Program Counter PC: saves the address of the instruction to be executed

[Detailed Process]

1. Interrupt request triggers: An external device or internal module issues an interrupt request, notifying the processor that a specific event has occurred. Interrupt detection and response: The processor detects the interrupt request at the appropriate time and determines whether to respond to the interrupt based on the interrupt controller’s settings. If the interrupt is allowed and has a higher priority, the processor will halt the current task and handle the interrupt event.

2. Save context: Before handling the interrupt, the processor needs to save the context information of the current task to correctly restore the interrupted task after the interrupt handling is completed. Context information includes the program counter (PC), register contents, etc.

3. Interrupt vector lookup: The processor uses the interrupt vector table (or interrupt vector address table) to determine the address of the interrupt handler. The interrupt vector table is a data structure that stores the addresses of interrupt handlers, finding the corresponding interrupt handler address based on the interrupt number or interrupt source identifier.

4. Execute interrupt handler: The processor jumps to the address of the interrupt handler to start executing the interrupt handling code. The interrupt handler is responsible for performing operations specific to the interrupt, such as reading data from external devices, updating status, triggering other tasks, etc. After handling the interrupt: When the interrupt handler completes related operations, the processor performs corresponding cleanup tasks, including clearing the interrupt flag and restoring the saved context information.

5. Restore context: The processor uses the previously saved context information to restore the state of the interrupted task. This includes restoring the program counter, register values, etc., to ensure that the task can continue execution from where it was interrupted.

6. Resume execution: After restoring the context of the interrupted task, the processor resumes executing the interrupted task, continuing the code flow that was interrupted.

It is important to note that the specific interrupt handling process may vary depending on the processor architecture, operating system, and application. The above steps provide a general outline of the basic process of interrupt handling.

Figure 3 Interrupt Architecture Diagram

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Figure 2.1 Musk’s post on social media platform X

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