Understanding the Debugging Interfaces of STM32 Cortex-M Cores

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When learning MCU development, debugging is definitely an essential step.

This article discusses the debugging interfaces related knowledge using STM32F1 and Cortex-M3 as examples (the principles are similar for other series chips/cores).

1

Overview

In STM32, there are many debugging components that can perform various debugging functions, including breakpoints, data watchpoints, flash address reloading, and various tracing.

STM32F1 uses the Cortex™-M3 core, which contains a hardware debugging module that supports complex debugging operations.

The hardware debugging module allows the core to stop during instruction fetches (instruction breakpoints) or data accesses (data breakpoints). When the core stops, both the internal state of the core and the external state of the system can be queried. After the query is completed, the core and peripherals can be restored, and the program will continue execution.

When the STM32F10x microcontroller is connected to the debugger and debugging begins, the debugger will perform debugging operations using the core’s hardware debugging module.

2

Debugging Block Diagram

The debugging block diagram of STM32F1 and Cortex™-M3:

Tip: The hardware debugging module included in the Cortex™-M3 core is a subset of the ARM CoreSight development toolset.

The ARM Cortex™-M3 core provides integrated on-chip debugging capabilities. It consists of the following parts:

• SWJ-DP: Serial/JTAG Debug Port

• AHP-AP: AHB Access Port

• ITM: Instrumentation Trace Macrocell

• FPB: Flash Patch and Breakpoint Unit

• DWT: Data Watchpoint and Trace

• TPUI: Trace Port Interface Unit (only supported on larger package chips)

• ETM: Embedded Trace Macrocell (supported on larger packages with pins for this function), specifically for the debugging features of STM32F1

• Flexible debugging pin assignments

• MCU debug box (supports low power modes, controls peripheral clocks, etc.)

3

Debugging Interfaces

STM32 supports two debugging interfaces:

• Serial Interface

• JTAG Debug Interface

The five general I/O ports of STM32 can be used as SWJ-DP (Serial/JTAG Debug) interface pins:

4

SWJ Debug Port (Serial Wire and JTAG)

The STM32 core integrates a Serial/JTAG debug interface (SWJ-DP). This is the standard ARM CoreSight debug interface, including the JTAG-DP interface (5 pins) and the SW-DP interface (2 pins).

1. JTAG Debug Interface (JTAG-DP) provides a 5-pin standard JTAG interface for the AHP-AP module.

2. Serial Debug Interface (SW-DP) provides a 2-pin (clock + data) interface for the AHP-AP module.

In the SWJ-DP interface, two pins of the SW-DP interface are multiplexed with some of the five pins of the JTAG interface.

SWJ Debug Port:

The above diagram shows that the asynchronous trace output pin (TRACESWO) and TDO are multiplexed. Therefore, the asynchronous trace function can only be implemented on the SWDP debug interface, and cannot be implemented on the JTAG-DP debug interface.

Mechanism for Switching Between JTAG-DP and SW-DP

The JTAG debug interface is the default debug interface. If the debugger wants to switch to SW-DP, it must output a specified JTAG sequence on TMS/TCK (mapped to SWDIO and SWCLK respectively), which disables JTAG-DP and activates SW-DP. This method can activate the SW-DP interface using only the SWCLK and SWDIO two pins.

The specified sequence is:

1. Output TMS (SWDIO) = 1 signal for more than 50 TCK cycles

2. Output 16 TMS (SWDIO) signals 0111100111100111 (MSB)

3. Output TMS (SWDIO) = 1 signal for more than 50 TCK cycles

5

Internal Pull-Up and Pull-Down on JTAG Pins

It is very important to ensure that the JTAG input pins are not floating, as they are directly connected to D flip-flops controlling the debug mode. Special attention must be paid to the SWCLK/TCK pins, as they are directly connected to the clock terminals of some D flip-flops.

To avoid any uncontrolled I/O levels, STM32 has embedded internal pull-ups and pull-downs on the JTAG input pins.

• JINTRST: Internal Pull-Up
• JTDI: Internal Pull-Up
• JTMS/SWDIO: Internal Pull-Up
• TCK/SWCLK: Internal Pull-Down

Once the JTAG I/O is released by user code, the GPIO controller regains control. The states of these I/O pins will revert to their reset states.

• JNTRST: Input with Pull-Up
• JTDI: Input with Pull-Up
• JTMS/SWDIO: Input with Pull-Up
• JICK/SWCLK: Input with Pull-Down

• JTDO: Floating Input

Software can use these I/O pins as ordinary I/O pins.

6

Using Serial Interface and Releasing Unused Debug Pins as Ordinary I/O Pins

To utilize the serial debug interface to free some ordinary I/O pins, user software must set SWJ_CFG=010 after reset, thereby releasing PA15, PB3, and PB4 for use as ordinary I/O pins.

During debugging, the debugger performs the following operations:

• At system reset, all SWJ pins are assigned as dedicated pins (JTAG-DP + SW-DP).

• In the system reset state, the debugger sends a specified JTAG sequence to switch from JTAG-DP to SW-DP.

• Still in system reset state, the debugger sets breakpoints at the reset address

• Releases the reset signal, and the core stops at the reset address.

• From here, all debugging communication will use the SW-DP interface, and other JTAG pins can be repurposed by user code as ordinary I/O pins.

Tip: This is where everyone needs to configure the relevant pins.

References:

1. Cortex™-M3 (r1p1 version) Technical Reference Manual (TRM)

2. ARM Debug Interface V5

3. ARM CoreSight Development Toolset (r1p0 version) Technical Reference Manual

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