Work
Mode
Thread mode: This mode is active when the processor is reset or exits from an exception. Code in this mode can be either privileged or user code, controlled by CONTROL[0].
Handler mode: This mode is entered when an exception (including interrupts) occurs, with all code having privileged access.
Code
Privileges
Privileged access: Full access rights to processor resources; this access mode is entered after a processor reset; to enter user mode, CONTROL[0] must be cleared.
User access: Access to most system registers is prohibited. One can only return to privileged mode by entering an exception (interrupt). If the access before entering the exception was user-level, it will automatically return to user mode upon exiting the exception unless CONTROL[0] was modified during the exception.
Work Status
Thumb state (normal execution instruction state) and debug state;
Registers
r0-r12: General-purpose registers, where r8-r12 can only be accessed by 32-bit instructions.
r13 (SP): Stack pointer; can switch between thread stack and main stack in thread mode, but only the main stack is used in handler mode. Only one of the two stacks is visible at any given time, and stack switching occurs automatically upon entering and exiting exceptions.
r14 (LR): Link register, saves the return address of a subroutine or exception (to achieve nesting, it must be pushed onto the stack).
r15 (PC): Program counter.
xPSR: Special-purpose program status register.
★ Exceptions ★
1. The processor automatically pushes the xPSR, PC, LR, r12, r3~r0 registers onto the current stack.
2. Read the vector table (if it’s a reset interrupt, update the SP value) 3. Update the PC value according to the vector table 4. Load the instruction at the new PC (steps 2, 3, and 4 occur simultaneously with step 1) 5. Update LR to EXC_RETURN (EXC_RETURN indicates the mode and stack to return to after exiting the exception).
1. Pop the 8 registers pushed onto the stack when entering the interrupt according to the stack indicated by EXC_RETURN.
2. Detect the IPSR register [8:0] bits to determine which exception to return to (this occurs during nested interrupts); if it is 0, return to thread mode.
3. Based on EXC_RETURN, choose the appropriate SP.
Tail-chaining: When an interrupt is currently being executed and another interrupt arrives with a lower priority than the executing interrupt (if there are other lower priority interrupts that have been pushed onto the stack, they must have a higher priority than these), the new interrupt is temporarily suspended, and after the current interrupt finishes executing, it directly enters the suspended interrupt without performing stack operations.
Late arrival: If the previous interrupt has not yet entered the execution phase (but the processor state has already been saved), and a higher priority interrupt arrives, the previous interrupt is preempted, and the later higher priority interrupt does not need to save the register state again.
Interrupts
In Cortex-M3, there are two concepts of priority – preemptive priority and response priority; some refer to response priority as ‘sub-priority’ or ‘secondary priority’. Each interrupt source must be assigned these two priorities.
Interrupts with high preemptive priority can be responded to during the handling of interrupts with low preemptive priority, i.e., interrupt nesting, or high preemptive priority interrupts can nest low preemptive priority interrupts.
When two interrupt sources have the same preemptive priority, these two interrupts will not have a nesting relationship. If one interrupt arrives while another is being handled, the later interrupt must wait until the previous one is finished before it can be processed. If both interrupts arrive simultaneously, the interrupt controller decides which to handle first based on their response priorities; if both their preemptive and response priorities are equal, the order in the interrupt table determines which one is handled first.
Source: uTank
http://www.cnblogs.com/utank/p/7943517.html
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