Introduction to Cortex-M0 Processor and ABMA Bus

The Cortex-M0 is the simplest 32-bit RISC processor in the ARM Cortex-M series, featuring a shared bus interface for instructions and data, as well as a three-stage pipeline structure that enhances instruction throughput and execution speed. It supports most 16-bit Thumb-1 instructions and some 32-bit Thumb-2 instructions, with interrupts including one non-maskable interrupt and 1 to 32 physical interrupts. The internal structure of the Cortex-M0 microprocessor is shown in Figure 1.1. The internal structure includes the processor core, AHB_Lite bus system, Nested Vector Interrupt Controller (NVIC), Wakeup Interrupt Controller (WIC), debug subsystem, and internal bus system.

Figure 1.1 Internal Structure of Cortex-M0 Microprocessor

The processor core is the “brain” of the Cortex-M0, containing registers, an Arithmetic Logic Unit (ALU), data paths, and control logic, employing a three-stage pipelined instruction channel structure. As shown in Figure 1.2, an instruction goes through three steps from fetching to execution, while the next instruction does not have to wait for the previous one to finish before starting its operation, but can begin its data transfer in the next clock cycle.

The bus system acts like a connector, establishing communication channels between the Cortex-M0 and various internal functional components for signal transmission and reception. The Cortex-M0 buses are all 32 bits wide, while AHB-Lite is the on-chip bus specification defined by ARM.

The Nested Vector Interrupt Controller (NVIC) is used to manage enabled interrupts and configure the priority of related interrupts. Each interrupt in the NVIC is assigned a preemptive priority and a response priority. When multiple interrupt requests arrive, they are compared based on preemptive priority; if they are the same, response priority is compared. After processing the interrupt request, the high-priority interrupt is sent to the processor for appropriate action. If the current processor is executing a lower-priority interrupt, a higher-priority interrupt can interrupt it, and after the high-priority interrupt is completed, it will return to continue the execution of the previous interrupt. The NVIC can accept up to 32 interrupt request signals and one non-maskable interrupt (NMI).

The debug subsystem is used to implement control and management of debugging, program breakpoints, and data monitoring points. When developers perform debugging work, they can pause the processor core at that point to analyze the processor’s state, register values, and flags. Hardware debugging tools include JTAG and SWD.

The Wakeup Interrupt Controller (WIC) is mainly used in low-power designs and is an optional module. Its low power consumption is achieved by shutting down most components, allowing the processor to enter sleep mode. Once an interrupt event is detected, the WIC sends a power-on request to the power manager, causing the processor to switch to normal operating mode.

• The register group is used to store data, including data that needs to be stored for a long time and intermediate data for processing calculations.

• Compared to external RAM or ROM, internal register access is faster.

• The register group adopts a load-save structure, where the processor does not operate directly on data in memory but first loads it into the register for processing, then writes it back to memory.

• The Cortex-M0 includes a register group and special registers, with R0-R12 being general-purpose registers, R0-R7 being low-privilege registers accessible by any instruction; R8-R12 are high-privilege registers that some Thumb instructions cannot access.

The register group of Cortex-M0 is shown in Figure 1.3:

Figure 1.3 Cortex-M0 Register Group

The Cortex-M0 processor provides a 4GB memory addressing space. Depending on different usage purposes, in conjunction with the Memory-map in the ARM Cortex-M0 user manual, this addressing space is roughly divided into regions, as shown in Table 2-1.

Table 2.1 Memory Addressing Space of Cortex-M0

The memory is roughly divided into the following areas:

Code Area: Used to store program code and data memory, typically composed of on-chip Flash.

SRAM Area: Used to store data, such as heap and stack, also used as a program code area, typically composed of on-chip memory like SRAM.

Peripheral Area: This area contains AHB peripherals, APB peripherals, and on-chip peripherals.

External RAM Area: This area is used to store large blocks of data or as a memory cache.

External Device Area: This area mainly maps addresses to external devices, connecting off-chip devices (also known as Off-chip Memory) such as SD cards, etc.

When designing the Cortex-M0 core, ARM defined the required signal ports and transmission characteristics, and based on this, established the AMBA bus protocol for interconnecting ARM processors with external devices. In the SOC of Cortex-M0, seamless access is achieved through AHB-Lite and APB-Lite protocols. The AHB bus is used for high-performance interconnections between modules, while the APB bus provides low-power interconnections for low-speed external devices.

The system architecture based on the AHB-Lite bus is shown in Figure 2-4.

Figure 2.1 System Architecture Based on AHB-Lite Bus

(1) Master. In this article, the master device refers to the Cortex-M0 processor core, whose main function is to perform calculations and issue address (HADDR), data (HWDATA), and control signals for data exchange with slave devices;

(2) Decoder. During a write operation, it enables a specific HSELx signal by receiving the HADDR address signal sent by the master device, thus driving a specific slave device, helping the Cortex-M0 core choose the slave device to access, sending data to that slave device and enabling it to perform the corresponding logical function. During a read operation, it sends a select signal to the multiplexer to complete the selection of data and signals output from a specific slave device;

(3) MUX. More accurately, it should be the slave device multiplexer, where the output signals from each slave device are given to the MUX, which selects one slave device’s output signal based on the select signal sent from the decoder and sends it to the master device.

(4) Slave. Slave devices all contain AHB-Lite ports, such as address (HADDR), data (HWDATA), and control ports, which the master device can access through these ports. The APB-Lite system architecture and functional components are basically the same as those of AHB-Lite, but their main difference is that the master device on AHB-Lite is the Cortex-M0 core, while the master device on APB-Lite is the AHB_to_APB Bridge. The APB bridge acts as a slave in the AHB-Lite system architecture, while in the APB-Lite architecture, it acts as the master, functioning as a “bridge” with simplified signal functions. For the Cortex-M0 core to access slave devices mounted on the APB bus, it must first access the APB bridge slave in the AHB-Lite system architecture, which can retain the transmitted address and data signals and simplify control signals, then act like a master device to send data and control signals to the APB-Lite system architecture. Conversely, when the Cortex-M0 core wants to read data from slave devices on the APB bus, it first sends the data to the APB bridge master in the APB-Lite architecture, which then sends the data to the master device Cortex-M0 as a slave in the AHB-Lite architecture.

The AHB-Lite protocol provides two global signals, as shown in Table 2-2.

Table 2-2 Global Signals in AHB-Lite

The master interface signals and their descriptions in the AHB-Lite protocol are shown in Table 2-3.

Table 2-3 Master Interface Signals in AHB-Lite

In Table 2-3, HADDR and HWDATA are the address and data signals of the bus, also the most basic signals for a transmission, while HWRITE, HSIZE, HTRANS, etc., are the control signals for that transmission. The HWRITE signal determines the direction of the transmission. HSIZE is a 3-bit signal that shows the width of the data during the transmission process. HTRANS is a 2-bit signal with four types of transmission modes: 00, 01, 10, 11, corresponding to wait, busy, non-sequential, and sequential transmissions respectively. In fact, the transmission types are only continuous and non-continuous; wait and busy are a type of transmission. When completing a data transmission process, if the signal is IDLE, it indicates that there is currently no data transmission, and the current transmission can proceed; if the signal is BUSY, it indicates that the master is currently in a transmission process and is busy, but the bus ownership has not been released yet, meaning it must wait until the transmission is complete before proceeding with the current transmission.

The slave interface signals and their descriptions in the AHB-Lite protocol are shown in Table 2-4:

Table 2-4 Slave Interface Signals in AHB-Lite

As shown in Table 2-4, slave devices mainly transmit data and status signals to the multiplexer, which then selects a slave device’s data to send to the master device based on the address and select signal.

The decoder and multiplexer signals in the AHB-Lite protocol and their descriptions are shown in Table 2-5.

Table 2-5 Multiplexer Signals in AHB-Lite Protocol

The transmission timing is the basic rule for the normal operation of each logic component. Only by adhering to the timing rules in the protocol can logical functions be designed to adapt to the CPU. In simple terms, the Cortex-M0 core has its own timing for reading and sending data, and the designed modules should also follow its timing, which is the fundamental requirement for the reliability of each module. AHB-Lite transmission includes two phases: the address phase and the data phase. The address phase generally lasts only one clock cycle, while the data phase may require multiple clock cycles to complete. There are two basic types of AHB-Lite transmission: non-waiting transmission and waiting transmission, as shown in Figures 2-5 and 2-6:

Figure 2.2 Basic Transmission Process of AHB-Lite without Wait

Figure 2.3 Basic Transmission Process of AHB-Lite with Wait

As shown in Figure 2.2, the AHB-Lite non-wait transmission process has data transitions synchronized with the rising edge of the clock. The gray spikes or abrupt states in the figure fit the actual situation where data signal transitions are not instantaneous; there is a very short indeterminate state during the transition from one state to another due to the time needed for MOSFETs to turn on and off and the charging and discharging of some capacitors not being instantaneous.

In Figure 2.2, the address cycle maintains one clock cycle, and after the rising edge of the clock arrives, address A is written to the address bus HADDR. In the data cycle, when the rising edge of the clock arrives, the HWRITE signal is low, indicating that this is a read transfer, so HRDATA will read the data corresponding to address A, Data(A), at the next rising edge of the clock. This type of transfer is emphasized as a non-wait transfer because a data transfer consists of an address cycle and a data cycle. If in the next cycle the HREADY signal is high, it indicates that the current transmission can continue, and thus the data cycle read/write operation will be completed immediately.

As shown in Figure 2.3, the address cycle and non-wait transfer are consistent, but in the next clock cycle of the address cycle, HREADY is low, indicating that the bus may be occupied or the slave device has not yet completed processing, so the current transfer needs to wait until the bus is free or the slave device is ready to perform the next read/write operation, then the HREADY signal will be raised to complete the data transmission process. The waiting signal HREADY for waiting transmission can be controlled logically by humans or autonomously by the Cortex-M0 core to ensure orderly transmission on the bus.

In actual transmission, it is not the case that all read operations are followed by all write operations; rather, read and write operations are often interleaved, as shown in Figure 2.4.

Figure 2.4 General Transmission Process of AHB-Lite

We divide the transmission into five segments:

T0-T1: Address cycle of A;

T1-T2: Data cycle of A; at this time, HREADY is high, and HWRITE is high, indicating a non-wait write operation transfer, so data corresponding to address A, DATA(A), is transmitted on the HWDATA bus. This is also the address cycle of B;

T2-T3: Data cycle of B; at this time, HREADY is high, and HWRITE is low, indicating a non-wait read operation transfer, so data corresponding to address B, DATA(B), is transmitted on the HRDATA bus. This is also the address cycle of C;

T3-T4: Data cycle of C; at this time, HREADY is low, and HWRITE is high, indicating a write operation, and this cycle is a waiting cycle, with no data transmission.

T4-T5: Data cycle of C; at this time, HREADY is high, so data corresponding to address C, DATA(C), is transmitted on the HWDATA bus.

Figure 2.5 Overall Architecture of SoC Based on Cortex-M0

This SoC’s overall architecture is divided into three parts: master device, AHB-lite, and mounted slave devices. The master device is the Cortex-M0 core, with ROM, GPIO, and AHB2APB Bridge mapped as slave devices to different address spaces, while the AHB bus acts as the master device, with UART, WDT, and TIMER as slave devices of the AHB bus.