Xilinx Zynq-7000 All Programmable SoC (AP SoC) series integrates the software programmability of ARM processors with the hardware programmability of FPGAs, enabling important analysis and hardware acceleration while also integrating CPU, DSP, ASSP, and mixed-signal functions in a single device. The Zynq-7000 devices are equipped with a dual-core ARM Cortex-A9 processor, which is integrated with programmable logic based on 28nm Artix-7 or Kintex-7, achieving excellent performance-to-power ratios and maximum design flexibility. The communication bus between the integrated CPU and FPGA allows for faster communication and a simpler information transfer structure. In simple terms, Xilinx’s chip not only saves costs but also improves performance. Is there really such a good thing? Yes, let me give you an example.
2/4 channels, maximum bandwidth 200MHz
The XC7Z020 SoC chip used in SDS1000X-E(X-C) features a dual-core ARM Cortex-A9 processor (PS) + FPGA based on the Artix-7 architecture (PL), where the processor part supports a maximum clock frequency of 866MHz. The FPGA part includes 85k logic cells, 4.9Mb Block RAM, and 220 DSP Slices, and supports common external memories such as DDR2/DDR3, which meets the needs for data acquisition, storage, and digital signal processing in digital oscilloscopes. At the same time, the PS (Processor System) and PL (Programmable Logic) parts of the Zynq-7000 are interconnected via a high-speed AXI bus, effectively addressing the bandwidth bottleneck in data transfer between the CPU and FPGA in traditional digital storage oscilloscopes, which helps reduce the dead time of digital oscilloscopes and improve waveform capture rates. Replacing the traditional CPU + FPGA discrete solution with a single SoC chip can also reduce the hardware layout area, facilitating the integration of high-performance processing systems into compact entry-level oscilloscopes.
The high-speed ADC chip used in SDS1000X-E(X-C) has a data interface in LVDS differential pair form, with each pair of LVDS having a rate of 1Gbps. The Zynq-7000 chip, with its programmable IO, can reach a maximum LVDS rate of 1.25 Gbps, ensuring stable and reliable reception of data sampled by the ADC. At the same time, the high-speed ADC data received by the FPGA needs to be written to memory in real-time. For an 8-bit, 1GSa/s ADC, the throughput of the output data is 1GByte/s. The Zynq-7000 supports common low-cost memories such as DDR2 and DDR3, with a maximum DDR3 interface rate of 1066MT/s, so a single DDR3 can meet the real-time storage requirements of the above ADC output data. Moreover, the Zynq-7000 supports PL sharing PS memory; as long as enough memory bandwidth is reserved for the PS part, the remaining bandwidth can be used to store ADC data, eliminating the need for additional memory on the PL side, reducing costs.
More importantly, based on the rich programmable logic resources in the Zynq-7000 (85k equivalent logic cells in XC7Z020), the SDS1000X-E(X-C) integrates a highly sensitive, low jitter, zero temperature drift digital triggering system, making triggering more accurate; various intelligent triggering functions such as slope, pulse width, video, timeout, under-amplitude, and pattern can help users isolate the waveforms of interest more precisely; bus protocol triggering can even use qualifying bus events (such as the start bit of an I2C bus or specific data of UART) as triggering conditions, greatly facilitating debugging.
Data Interaction
As the complexity of digital oscilloscope design increases and the processing power of processors improves, the bus structure has increasingly become a bottleneck for system performance. Traditional entry-level digital oscilloscopes use low-cost embedded processors as control and processing cores, and low-cost FPGAs for data acquisition and storage, interconnected via a parallel local bus, where the processor acts as the master device and the FPGA as the slave device; other processor peripherals, such as FLASH, USB controllers, etc., are also connected to the bus, as shown in Figure 4.
The biggest problem with this interconnection method is the low data throughput. First, because the local bus is generally an asynchronous bus, ideally, a read/write access requires at least 3 cycles (1 setup cycle, 1 access cycle, and 1 hold cycle). For a 16-bit wide local bus with an external bus frequency of 100MHz, the ideal maximum bus access throughput is 66MB/s; second, because read and write operations share a set of address and data buses, it is half-duplex operation; third, multiple slave devices compete for the bus, thus reducing the effective data throughput for each slave device. For a digital oscilloscope with a sampling rate of 1GSa/s, the time to sample 10M points is only 10ms, but the time used to transmit 10M points (based on the ideal 66MB/s bus throughput) takes at least 150ms, which is 15 times the data sampling time. In other words, even without considering the data processing time, the dead time reaches 15/16 = 93.75%.
The SDS1000X-E(X-C) adopts the Zynq SoC architecture, with a high-speed AXI bus interconnecting the processor (PS) and FPGA (PL), effectively solving the bandwidth bottleneck in data transfer between the two, greatly improving data throughput and reducing the dead time of the oscilloscope. The Zynq-7000 employs four AXI-HP ports, each supporting a maximum 64-bit width and a clock frequency of up to 250MHz; at the same time, the read and write channels are separated, allowing for full-duplex operation; the PS and PL are point-to-point transmission, without bus competition with other devices. Using a single HP port for data transmission, its throughput can easily reach 1GB/s in both directions, and the total read and write rate of four ports can exceed 8GB/s, far greater than the transmission rate of the local bus.
Digital Signal Processing
The SDS1000X-E(X-C) is equipped with many practical and powerful digital signal processing functions, such as FFT supporting 1M points of computation, enhanced resolution (Eres mode, only supported by SDS1000X-E), serial protocol decoding of 14M full sampling points, various measurements and mathematical operations of 14M full sampling points, greatly improving the digital signal processing capability of entry-level digital oscilloscopes.
The rich hardware resources of the Zynq-7000 provide strong support for the digital signal processing functions of the SDS1000X-E(X-C). The XC7Z020 SoC chip used in SDS1000X-E(X-C) features a dual-core ARM Cortex-A9 processor in the PS part with a maximum clock frequency of 866MHz, while the parallel co-processor NEON can perform digital signal processing at the software level; the PL part has 220 DSP Slices and 4.9Mb Block RAM; combined with the high throughput of the data interface between PS and PL, we can flexibly configure different hardware resources for different digital signal processing tasks.
Complex computational instructions suitable for software implementation can be realized on the PS side, such as measuring the rising edge of a signal; functions that require a large number of multiply-accumulate operations and highly depend on hardware resources can be implemented on the PL side, such as interpolation filtering commonly used in oscilloscopes.
Some complex functions can utilize the high data bandwidth between PS and PL for collaborative processing. For example, FFT operations can be hardware accelerated on the PL side using abundant DSP Slices and Block RAM resources to build a co-processor for basic FFT operations, while the PS side performs complex window function calculations, plotting, UI, etc. Based on this collaborative processing architecture, the SDS1000X-E(X-C) supports FFTs of up to 1M points, achieving extremely high spectral resolution while significantly accelerating spectral refresh rates. Figure 6 shows a comparison of spectral resolution for 16k point and 1M point FFTs performed on the SDS1000X-E(X-C). In this example, we input a dual-tone signal with frequencies of 100MHz and 100.05MHz into the oscilloscope. The spectrum obtained from the 16k point FFT does not allow us to distinguish the two sine signals that are so close together, as they appear as a single frequency; however, the spectrum from the 1M point FFT shows a much finer spectrum and signal processing gain, as can be seen from the horizontally expanded graph by 100 times, where the two sine signals spaced 50kHz apart can be well distinguished.
Similarly, the SDS1000X-E(X-C) has many high-performance digital signal processing capabilities obtained through collaborative processing between PS and PL. For instance, the SDS1000X-E(X-C) can perform various measurements and serial protocol decoding on 14M full sampling points, which many mid-to-high-end oscilloscopes cannot achieve. In Figure 7, the upper two images show the measurement results for a 10ns rising edge from a mainstream mid-range oscilloscope, while the lower two images show the measurement results for the same signal from the SDS1000X-E(X-C). It can be seen that at a short time base, both measurement results are quite accurate and close to the actual rise time; however, at a longer time base, the upper right image shows that the oscilloscope can only display “< 48ns” for the measurement result at 100us/div, despite having a raw sampling rate of 1GSa/s, indicating that it is measuring not the original waveform data but the data compressed and mapped onto the screen. The lower right image shows the measurement result of the SDS1000X-E(X-C) at a time base of 1ms/div, where the sampling rate is also 1GSa/s, but the displayed measurement accuracy still reaches 1ns, which can reflect the signal parameters more accurately.
The SDS1000X-E(X-C), based on full sampling point digital signal processing and a storage depth of up to 14M points, allows users to observe the overall signal at a large time base while still obtaining detailed processing results; at the same time, its processing method based on the Zynq architecture optimizes the performance and speed of signal processing, achieving better real-time performance and flexibility.
In summary, this example illustrates that in products that originally use ARM + FPGA solutions, using Zynq can not only reduce costs but also significantly improve performance. This allows the SDS1000X-E(X-C), positioned as an entry-level oscilloscope, to reflect some indicators and functions that are typically found only in mid-to-high-end digital oscilloscopes.
