Understanding Cortex-M Interrupts and FreeRTOS Interrupt Priority Configuration

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Author | strongerHuang

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If the CPU has no interrupts, can you imagine what it would be like?

It would just be a while loop, unable to handle tasks in a timely manner, let alone have the current RTOS (RTOS also requires interrupts to be realized).

Next, let’s talk about the interrupts of Cortex-M and the principles of FreeRTOS interrupt priority configuration.

1About Cortex-M3 Processor

Before writing this article, let’s write some relevant extended content, this article combines the core of Cortex-M3 with STM32 for discussion.

STM32 belongs to the ARM Cortex-M series processors, for example: STM32F1 data Cortex-M3, STM32F7 data Cortex-M7.

You can refer to my previous article “Understanding ARM Processors from Cortex-M to Cortex-A“, to learn about the types of ARM processors.

This article mainly discusses interrupt control related content based on Cortex-M3 and the STM32F1 series processors. Other Cortex-M series or STM32 series related to interrupts are similar.

Cortex-M3 is just a core of STM32F1. Conversely, STM32F1 is a chip that adds some peripherals (such as: USART, AD, etc.) based on Cortex-M3.

2Cortex-M Interrupt Control

NVIC: Nested Vectored Interrupt Controller, that is, the nested vector interrupt controller.

We are quite familiar with NVIC in STM32, when programming we always configure NVIC when using interrupts.

And the NVIC in STM32F1 is part of Cortex-M3, not a peripheral added by STM32.

NVIC vector interrupt controller is an inseparable part of Cortex‐M3, it is tightly coupled with the CM3 core logic, with some parts even intertwined.

Therefore, the NVIC related registers are located in the Cortex-M manual. To discuss STM32’s interrupt control, we must start with the NVIC of Cortex-M3.

1. Interrupt Input Vector Table

The NVIC of Cortex-M3 supports 1 to 240 interrupt inputs, such as xxxIRQs in STM32, which is the interrupt vector table, the specific value is determined by the chip manufacturer during chip design.

For example, the interrupt and exception vector table of STM32F1:

2. Difference Between Interrupts and Exceptions

Many beginners do not know what is an interrupt? What is an exception? Some even directly refer to both interrupts and exceptions as “interrupts”.

Interrupts and exceptions actually have differences, but also have connections, what we commonly refer to as interrupts actually includes exceptions. An exception can be understood as the MCU or program being in some abnormal state.

To distinguish, look at the vector table above, the upper part with a gray background is an exception, the lower part in white is an interrupt.

Exceptions belong to Cortex‐M3 core, while interrupts belong to the MCU (STM32) (determined by the manufacturer).

So:

1. From the perspective of Cortex‐M3 core, interrupts like USART in STM32 are considered external interrupts.

2. From the perspective of STM32, EXTI external pin interrupts are considered interrupts.

3. Priority

For Cortex-M3, each external interrupt has a corresponding priority register.

Each register occupies 8 bits, but allows at least using the highest 3 bits, while in STM32F1, the high 4 bits are used (which means we can divide into 16 priorities).

Priorities can be divided into high and low levels, namely preemptive priority and sub (response) priority.

Tip:

1.In STM32, the smaller the interrupt priority value, the higher the priority.

2.Priority grouping: Cortex-M3 and M4 have grouping functions, meaning there are preemptive priorities and response priorities, as shown below:

Some cores do not have this function, such as Cortex-M0.

3. Reference Material

You can refer to “Cortex-M3 Authority Guide”

STM32’s core programming manual:

http://www.st.com/stonline/products/literature/pm/15491.pdf

3FreeRTOS Interrupt Priority Configuration

This section discusses the maximum interrupt priority configuration problem of FreeRTOS, that is, in the FreeRTOSConfig.h configuration file:

configMAX_SYSCALL_INTERRUPT_PRIORITY

Do you know the meaning of the configured value? Here, it is necessary to understand in conjunction with NVIC related content.

As mentioned above, in STM32, the high 4 bits of NVIC priority are used, and we need to configure the high 4 bits (the low 4 bits are not used).

Looking at the above picture, do you understand? The value above is 95, but the priority it represents is 5.

The meaning of this configuration value is roughly: the interrupt you use in your code (for example, USART1_IRQn) needs to have a priority greater than 5 to work.

For the configuration below, a priority of 2 would not work (of course, grouping also involves grouping issues).

For more information about FreeRTOS maximum priority configuration, you can refer to:

https://www.freertos.org/RTOS-Cortex-M3-M4.html

Finally, once again remind:

FreeRTOS task priority is such that the larger the value, the higher the priority, and needs to be distinguished from CM3 interrupt priority.

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