Application and Precautions of Cortex-M Interrupts in RTOS

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Author | strongerHuang

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Can you imagine what happens if the CPU has no interrupts?

It would just be a while loop, unable to handle tasks in a timely manner, let alone have the current RTOS (RTOS also needs interrupts to function).

Next, let’s discuss the application and precautions of Cortex-M interrupts in RTOS.

About Cortex-M Processors

First, let’s introduce some content related to Cortex-M processors, this article will discuss it in conjunction with the STM32 based on the Cortex-M3 core.

STM32 belongs to the ARM Cortex-M series processors, for example: STM32F1 data Cortex-M3, STM32F7 data Cortex-M7.

Application and Precautions of Cortex-M Interrupts in RTOS

You can refer to my previous article “Understanding ARM Processors from Cortex-M to Cortex-A“, to learn about the types of ARM processors.

This article mainly discusses interrupt control related content with Cortex-M3 based STM32F1 series processors as an example. The interrupt content for other Cortex-M series or other STM32 series is similar.

Cortex-M3 is just one core of the STM32F1. Conversely, STM32F1 is a chip that adds some peripherals (such as: USART, AD, etc.) based on Cortex-M3.

Cortex-M Interrupt Control

NVIC: Nested Vectored Interrupt Controller, which is the nested vector interrupt controller.

We are quite familiar with NVIC in STM32, when programming, we will configure NVIC when using interrupts.

And the NVIC in STM32F1 is part of the Cortex-M3, not a peripheral added by STM32.

The NVIC vector interrupt controller is an inseparable part of Cortex-M3, tightly coupled with the CM3 core logic, with some parts even merging together.

Therefore, the registers related to NVIC are located in the Cortex-M manual. To discuss STM32’s interrupt control, we must start from the NVIC of Cortex-M3,

1. Interrupt Input Vector Table

The NVIC of Cortex-M3 supports 1 to 240 interrupt inputs, such as xxxIRQs in STM32, which is the interrupt vector table, and the specific values are determined by the chip manufacturer during chip design.

For example, the interrupt and exception vector table of STM32F1:

2. Difference Between Interrupts and Exceptions

Many beginners do not understand what is an interrupt? What is an exception? Some even directly refer to interrupts and exceptions generically as “interrupts”.

Interrupts and exceptions actually have differences, but also connections; what we commonly refer to as interrupts actually includes exceptions. Exceptions can be understood as the MCU or program being in a certain abnormal state.

To distinguish, look at the vector table above, the upper part with a gray background is exceptions, the lower part with a white background is interrupts.

Exceptions belong to Cortex-M3 core, while interrupts belong to the MCU (STM32) (determined by the manufacturer).

So:

1. From the perspective of Cortex-M3 core, interrupts like USART in STM32 belong to external interrupts.

2. From the perspective of STM32, EXTI external pin interrupts belong to interrupts.

3. Priority

For Cortex-M3, each external interrupt has a corresponding priority register.

Each register occupies 8 bits, but allows at least only the highest 3 bits to be used, in STM32F1 the high 4 bits are used (which means we can divide into 16 priorities).

Priorities can be divided into high and low segments, respectively preemption priority and sub (response) priority.

Tip:

1.In STM32, interrupt priority the smaller the value, the higher the priority.

2.Priority grouping: Cortex-M3 and M4 have grouping functions, that is, there are preemption priorities and response priorities, as shown in the following figure:

However, some cores do not have this feature, such as Cortex-M0.

3. Reference Materials

You can refer to “Cortex-M3 Authority Guide”

STM32’s core programming manual:

http://www.st.com/stonline/products/literature/pm/15491.pdf

RTOS Interrupt Priority Configuration

This section discusses the maximum interrupt priority configuration issue of FreeRTOS, which is in the FreeRTOSConfig.h configuration file:

configMAX_SYSCALL_INTERRUPT_PRIORITY

Do you know the meaning of the configured value? Here, we need to understand it in conjunction with NVIC related content.

As mentioned earlier, in STM32, the high 4 bits of NVIC priority are used, and we need to configure the high 4 bits when configuring (the low 4 bits are not used).

Look at the figure, do you understand? The above value is 95, but the represented priority is 5.

The meaning of this configuration value is roughly: the interrupt you use in your code (for example, USART1_IRQn) must have a priority greater than 5 to be valid.

For the following configuration, a priority of 2 would not work (of course, grouping issues are also involved).

For more information about FreeRTOS maximum priority configuration, you can refer to:

https://www.freertos.org/RTOS-Cortex-M3-M4.html

Finally, again remind:

FreeRTOS task priority is the larger the value, the higher the priority, which needs to be distinguished from CM3 interrupt priority.

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