For ARM processors, interrupts provide the processor with a sense of touch, allowing it to perceive changes in the external environment and process them in real time. This series of blog posts aims to introduce the handling of interrupts in ARM SoCs, specifically focusing on the ARM Cortex-A series processors.

The ARM Cortex-A series processors provide four pins for the SoC to realize the transmission of external interrupts, which are:

• nIRQ: Physical normal interrupt

• nFIQ: Physical fast interrupt

• nVIRQ: Virtual normal interrupt

• nVFIQ: Virtual fast interrupt

As shown in the figure below:

Among them, virtual interrupts are added for virtualization purposes. In this series, we will not discuss virtual interrupts but will focus on the knowledge related to physical interrupts.

In the ARM SoC system, there are multiple peripherals, each of which may generate interrupts to be sent to the ARM CPU, waiting for CPU processing.

The ARM CPU provides only two signals for interrupts: one nIRQ and one nFIQ. Therefore, there needs to be an interrupt controller to serve as an intermediary bridge, collecting all interrupt signals from the SoC, arbitrating to select the appropriate interrupt, and then sending it to the CPU, waiting for CPU processing. As shown in the figure below:

The bridging device in between is the well-known GIC, General Interrupt Controller, launched by ARM.

The GIC is actually an architecture that has gone through several versions: GICv1 (deprecated), GICv2, GICv3, and GICv4. For different GIC versions, ARM has designed corresponding GIC IPs.

• GIC400, supports GICv2 architecture version.

• GIC500, supports GICv3 architecture version.

• GIC600, supports GICv3 architecture version.

The core function of the GIC is to manage the interrupt sources of peripherals in the SoC and provide software with the ability to configure and control these interrupt sources.

When the corresponding interrupt source is valid, the GIC decides whether to send that interrupt signal to the CPU based on the configuration of that interrupt source. If multiple interrupt sources are valid, the GIC will also arbitrate to select the highest priority interrupt to send to the CPU.

When the CPU receives the interrupt sent by the GIC, by reading the GIC registers, it can determine where the interrupt is coming from and thus take appropriate action.

After the CPU has processed the interrupt, it will inform the GIC, which is essentially accessing the GIC registers to indicate that the interrupt processing is complete. Upon receiving this information, the GIC will cancel that interrupt source to prevent it from being sent to the CPU again and allow interrupt preemption.

Next, we will first introduce the relevant knowledge of GICv2, and then introduce the currently mainstream GICv3.