Compiled by: Technology makes dreams greater | Li Xiaoyao

Link: https://itexp.blog.csdn.net/article/details/85029696

Problem

Recently, while using the STM32F3 chip, I encountered a problem: If the frequency of external interrupts is fast enough, how to handle the new interrupt if the previous one has not been processed?

During debugging, I found that interrupts can be in suspended, activated, disabled, and other states. What are these states for? They are common to the Cortex-M core, so let’s understand them at the Cortex-M core level instead of focusing on the specific STM32 MCU!

Introduction

Interrupts (also known as “exceptions”) are a common feature of microcontrollers. Interrupts are generally generated by hardware (such as peripherals, external pins), and once an interrupt is generated, the CPU will interrupt the current program execution flow to handle the operations specified by the interrupt service.

All Cortex-M cores will include a component for interrupt handling: NVIC (Nested Vectored Interrupt Controller). It handles interrupts and other events that need service (such as SVC instructions), commonly referred to as exceptions (according to ARM, interrupts are also a type of exception).The NVIC of Cortex-M3 and Cortex-M4 supports up to 240 IRQs (interrupt requests), 1 Non-Maskable Interrupt (NMI), 1 SysTick timer interrupt, and multiple system exceptions. The Cortex-M0 supports up to 32 IRQs, 1 NMI, 1 SysTick timer interrupt, and multiple system exceptions.

• IRQ: Most are generated by timers, IO ports, communication interfaces, and other peripherals.

• NMI: Usually generated by watchdog timers or power failure detectors.

• Others: Mainly from the system kernel.

Note that the Cortex-M mentioned in this article mainly refers to Cortex-M3 and Cortex-M4.Cortex-M0, Cortex-M0+, and Cortex-M1 are based on ARMv6-M. Compared to Cortex-M3 and Cortex-M4, their instruction sets are smaller. Additionally, Cortex-M1 is specifically designed for FPGA applications and does not have an independent MCU.

Types of Exceptions

Among the exceptions handled by the Cortex-M processor, numbers 1~15 are system exceptions, while those 16 and above are interrupt inputs. All interrupt-level exceptions have programmable priorities. Some system exceptions have fixed priorities. ARM provides the following table:

For the Cortex-M series core, ARM provides a set called CMSIS. Currently, all MCUs use CMSIS as a programming basis. In CMSIS-Core, interrupt identifiers have an interrupt enumeration implementation, starting from value 0 (representing interrupt #0). The system exception numbers are negative. Specifically:

The reason CMSIS-Core uses a different numbering system is to slightly improve the efficiency of some APIs. The numbering and enumeration definitions of interrupts are device-specific and are located in header files provided by the microcontroller vendor in a typedef segment named IRQn.

Interrupt Handling (Exception Handling)

When a certain internal or external event occurs, the MCU’s interrupt system will force the CPU to pause the currently executing program and switch to handle the interrupt event. After the interrupt has been handled, it returns to the interrupted program and continues execution.

The main program is executing when it encounters an Interrupt Request (IRQ), it pauses the main program execution to execute the Interrupt Service Routine (ISR), which is called a response. After the ISR completes, it returns to the breakpoint of the main program and continues executing. Multiple interrupts can be nested. A lower-priority interrupt being executed can be interrupted by a higher-priority interrupt, and after executing the higher-level interrupt, it returns to the lower-level interrupt to continue execution.

Interrupt Management

Most registers used to manage interrupts are located in the NVIC (Nested Vectored Interrupt Controller) and SCB (System Control Block). In fact, the SCB is implemented as part of the NVIC, but in CMSIS-Core, it is defined in a separate structure. Additionally, there are interrupt masking registers in the processor core: PRIMASK, FAULTMASK, BASEPRI.

The NVIC and SCB are located in the system control space, starting from address 0xE000E00, with a size of 4KB. The SCB also includes the SysTick timer, memory protection unit, etc.

Priority

This part is not discussed for now!

Interrupt Input and Pending

In the Cortex-M core, each interrupt has multiple attributes:

• Each interrupt can be disabled (default) or enabled.

• Each interrupt can be pending or un-pending.

• Each interrupt can be active or inactive.

These state attributes have various possible combinations. For example, while handling an interrupt, it can be disabled. If a new request for the same interrupt is generated before exiting the interrupt, since the active interrupt is disabled, it will be in a pending state.

The NVIC is designed to support peripherals that generate pulse interrupt requests as well as those that generate level interrupt requests. No NVIC register configuration is needed to select one of the interrupt types. For pulse interrupt requests, the pulse width must be at least one clock cycle; for level-triggered requests, the requesting peripheral must maintain the level signal until the request is cleared in the ISR (e.g., writing to a register to clear the interrupt request). Although the external interrupt request may be low-active on the I/O pin, the request signal received by the NVIC is high-active!

The pending state of an interrupt is stored in the programmable register of the NVIC. Once the NVIC’s interrupt input is confirmed, it will trigger the pending state of that interrupt. Even if the interrupt request is canceled, the pending state will still be high. This allows the NVIC to handle pulse interrupt requests.

The pending state means that the interrupt is placed in a state waiting for the processor to handle it. In some cases, the processor may handle it while the interrupt is pending. However, if the processor is already handling another higher or same-priority interrupt, or if the interrupt is masked by some interrupt masking register, then the pending request will remain until all other interrupt handling is finished or the interrupt mask is cleared.

In traditional ARM processors, if a peripheral generates an interrupt, it must maintain the interrupt request signal until it is processed.

When the interrupt begins processing the interrupt request, the interrupt request signal will be automatically cleared. While the interrupt is being processed, it will be in an active state.When the interrupt is in an active state, the processor cannot process the same interrupt request again until the completion of the interrupt and the return from the exception.

The pending state of an interrupt is located in the interrupt pending state register, and software can reset these registers. Therefore, the pending state of an interrupt can be manually cleared or set. If the interrupt request occurs while the processor is handling another higher-priority interrupt, and the pending state is cleared before the processor responds to that interrupt request, then that interrupt will be canceled and will not be processed again.If a certain interrupt request is continuously maintained, even if the software attempts to clear the pending state, the pending state will still be set again.If the interrupt has been processed but the interrupt source continues to maintain the interrupt request, then this interrupt will enter the pending state again and be processed againFor pulse interrupt requests, if the interrupt request signal is generated multiple times before the processor starts processing, they will be treated as a single interrupt request.The interrupt pending state can be set again while it is being processed. If a new request is generated while the previous interrupt request is being processed, this may trigger a new pending state. The processor needs to handle this interrupt again after the previous ISR ends.Even if the interrupt is disabled, its pending state can still be set. In this case, if the interrupt is enabled later, it can still be triggered and processed. This situation may not be what we want, so we need to manually clear the pending state before enabling the NVIC interrupt.

Summary

NVIC requires setting the preemption priority and response priority (also called sub-priority) for each interrupt. Multiple interrupts will first compare the preemption priority, and if the preemption priorities are the same, they will compare the response priority. High preemption priority can interrupt low preemption priority, but high response priority with the same preemption priority cannot interrupt low response priority.

1. High priority preemption can interrupt low priority preemption that is currently in progress.

2. For interrupts with the same preemption priority, high response priority cannot interrupt low response priority interrupts.

3. For interrupts with the same preemption priority, if two interrupts occur simultaneously, the one with the higher response priority is executed first.

4. If two interrupts have the same preemption priority and response priority, the one that occurs first is executed first.

References

1. The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors, 3rd Edition

2. The Definitive Guide to the Cortex-M0

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