RK3588 Course Series: LPDDR4 Memory Control Circuit Design and Parameter Optimization

This course series uses RK3588 chip as the core hardware design, based on the latest version of Cadence Allegro Allegro X software, to perform a complete end-to-end project design and simulation of the system’s on-chip resources, interface circuit design, and various commonly used peripheral resources for chip expansion. It integrates the latest software features and techniques into daily designs, reducing project redundancy and accelerating rapid project delivery.

LPDDR4 Memory Control Circuit Design and

Parameter Optimization

This course starts with the classification and functions of commonly used memory, including DDR4 memory control technology, comparison of LPDDR4 and DDR4 memory technologies, RK3588 LPDDR4 dual-channel memory technology, changes in LPDDR4 architecture, comparison of configuration options, grouping of memory control signals, and key points in memory circuit design.

Come click the video below to watch!

On June 30 (Friday) from 15:00 to 16:00, Teacher Li Zeng will appear in the live broadcast room, focusing on sharing experience in RK3588 peripheral circuit design techniques.

It will address design techniques for LPDDR4, EMMC, MIPI CSI, VO HDMI, VI-Camera_MIPI-CSI, and VO-HDMI 2.1 circuits, as well as issues and parameters encountered in design.

A detailed analysis of the system hardware design ideas, circuit interfaces, and on-chip control interface circuit design for RK3588 DVR will be provided.