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Abstract
In the automotive industry, reducing development costs is crucial. The development of electrical hardware is an expensive and time-consuming process that involves many stages (such as prototyping, electrical testing, mechanical testing, lifecycle testing). There is a growing demand to use virtualization to improve the cost-effectiveness of embedded software development and testing stages. With this approach, fewer prototypes need to be manufactured, as simulations can quickly and efficiently identify most potential faults without the need to build hardware prototypes. Renode is an open-source embedded system simulation framework that aids in software-based testing. The main objective of this article is to explore the usability of this framework in automotive applications.
(Translator’s note: Renode uses QEMU’s processor model; discussions about QEMU are referenced in our video account and public account; we also undertake custom development based on Renode and QEMU virtualization, welcome to contact us.)
Keywords: Embedded system simulation; MCU microcontroller virtualization; Software-in-the-loop SIL
1. Introduction
The electronic control units installed in new vehicles usually need to run some embedded software to ensure the proper functioning of the controllers. The development time for these controllers is long, and repetitive prototyping and testing increase costs.
In addition to embedded software development, developing the necessary hardware is also important. However, this task requires continuous prototyping and redesign based on testing results, requiring multiple iterations. It is also time-consuming and costly. The goal of simulating hardware and software together is to verify that the hardware and software can work correctly. This task is traditionally performed after the prototype hardware is completed, but if such verification can be done in a virtual environment, it can reduce the costs of prototyping and any iterations as well as the time required for development.
Electronic control units (ECUs) in automotive electronic systems may experience functional failures due to interference between the analog signals generated on the circuit and the binary signals used in the control unit’s microprocessor [1]. Currently, the industry tests the functionality of such failures experimentally, which is time-consuming and may occur late in the development stage (when there is a physical prototype), and correcting and retesting is very time-consuming. Due to hardware supply difficulties, development is often delayed, and debugging on real hardware is also very challenging. For all these reasons, testing the functional robustness of automotive electronic systems is costly and time-consuming [2].
Therefore, the automotive industry is very eager to have an industrially applicable virtual robustness testing method that can test the functional robustness of automotive electronic systems through computer simulation [3,4,5,6].
A software toolbox is needed that allows for virtual functional testing of automotive electronic system control units. The goal is to study a simulation method suitable for virtual functional testing of electronic components [7]. This can be important in all areas:
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Early detection of design errors;
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Shortening development time;
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Improving test coverage and test efficiency;
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Significantly reducing testing costs;
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Minimizing the use of hardware elements.
This solution can be used in any electronic system design process that requires functional testing of control units, joint simulation of analog and digital circuits, or robust design and operation. Unfortunately, there is a lack of information in the scientific literature about applicable software solutions. Most available tools provided by teams like Synopsys and Cadence focus on semiconductor design and instruction set verification. Other simulators, such as LabCenter Proteus and DesignSoft TINA, are not open-source and are difficult to extend their microcontroller models [8,9]. Thus, the aim of this study is to explore whether it is possible to apply Renode to handle the virtualization of the electrical development toolchain.
(Translator’s note: Simulators provided by Synopsys, MachineWare, etc., are chip-level, while simulators like Proteus and TINA focus on PCB-level. We undertake custom development services for virtualization at both chip and PCB levels; welcome to contact us for more information.)
2. What is Renode?
Renode is an open-source simulation software solution for embedded platforms. It is an instruction set simulator that supports various out-of-the-box architectures, such as x86 (Intel Quark), ARM Cortex-A, Cortex-M, SPARC, and RISC-V, and due to its open-source nature, it can be further extended. It can be used to assemble virtual systems on chips from building blocks, such as various types of microcontrollers (e.g., Cortex-M, Cortex-A) and different peripheral models (Figure 1). Therefore, it can also simulate microcontrollers used for automotive control. Untouched production firmware can run against the simulated cores, peripherals, and even configured sensors and actuators. The parameters of the simulated embedded systems (e.g., memory addresses, peripherals, etc.) are defined in text-based configuration files, while the functionality is modeled in C#.
Figure 1. Microcontrollers and connected peripherals.
Using Renode, fast software development and debugging capabilities can be achieved without evaluating hardware, just like in standard IDE design processes. Most integrated development environments can be used, with the only requirement being the ability to connect to a GDB server for debugging.
(Translator’s note: Achieving fast software development and debugging capabilities without evaluating hardware is the overall goal of the global virtual prototyping industry.)
3. Renode System as a Virtual Platform
The platforms in Renode model the system bus of the machine (identified as sysbus) as a central building block for connecting peripherals. All peripherals can be accessed from anywhere in the created platform.
Actual hardware may use various intricate connection buses, but the same platform in Renode uses only a single bus. This simplification usually does not affect the behavior of the simulation in any way, as the interconnection structure in the SoC is hidden from a software perspective.
Configuration files are necessary to define the simulated MCU and development board. Using these text-based configuration files, the environment can be automatically launched.
Renode simulation typically involves several key files that work together to define and execute the simulation environment in Renode. The files typically involved are shown in Figure 2.
Figure 2. Files typically involved in Renode simulation.
Renode script files (with the .resc extension) contain the commands needed to create the virtual machine, load board files, and other logging extensions. This enables automation of command-line operations. Renode platform definition files (with the .repl extension) include descriptions of the MCU (e.g., CPU and peripherals) and the board. This script loads the processor descriptions and the configuration of the system hardware connections (e.g., GPIO connected to LEDs). Renode can also load custom peripheral models developed in Verilog or C++ [10].
4. Implementation of STM32F4 Discovery Board
The STM32F4 series is a range of 32-bit microcontrollers developed by STMicroelectronics. These microcontrollers are based on high-performance ARM Cortex-M cores with rich peripherals. The STM32F4 Discovery Board is a popular development board that leverages the capabilities of the STM32F407 microcontroller (embedded debugging tools, digital accelerometers, LEDs, buttons). This board is designed to help users easily develop and test applications, especially those involving audio processing.
This article uses the STM32F4 Discovery Board simulation to test the simulation setup using Renode. Figure 3 shows the memory address space of the Cortex-M4 CPU, with the configuration parameters of the profile being the same as below [11].
Figure 3. Block diagram of the Cortex-M4 CPU (top left) and memory address space.
In Renode, once the virtual machine is created, it only contains one peripheral, the system bus, referred to as sysbus. At this point, there is no CPU or memory, so the machine is not ready to execute any code. Renode uses a text-based format to describe the platform.
After loading the necessary board files using predefined platform definitions (platform description files) in the Renode terminal window, all peripherals are configured, and the virtual machine is ready for use. All configured peripherals can be listed, and binary files can be loaded for testing and debugging against the simulation (Figure 4).
Figure 4. Configured peripherals defined for STM32F4 in the Renode terminal window.
5. Debugging
Virtual debugging is the most important function necessary for handling ECU development virtualization. The virtual machine can be used to debug binary code using the GDB remote protocol. General GDB functions (such as breakpoints, stepping, memory access) can be used to check the binary code against the virtual hardware while the binary code runs. There is a significant difference in time requirements between debugging on real hardware and virtual debugging; the debugging process is transparent for the simulated machine, as virtual time does not advance when the simulated CPU stops.
Due to deterministic time flow, the process is simpler; the debugging process can stop the entire system simultaneously. It is very suitable to be part of automated testing scenarios, such as running in the background on CI servers. Renode integrates with the Robot Framework test suite, allowing it to be used with other test automation environments and providing user-friendly scripts for running tests (Figure 5).
Figure 5. The process of development and testing using Renode.
Assuming the executed binary file (compiled .elf file) contains symbol mappings (which is usually the case during development), it can track its execution, obtain detailed logs (including the names of executed functions, peripheral access, and opcode counts), generate code coverage reports, and use advanced GDB integration. Renode also comes with a built-in disassembler and metrics analyzer, can simulate device elements using labels, integrate with external analyzers like Wireshark, and allow the use of hooks to monitor or change the execution of the binary file, such as triggering software behavior by deceiving register/memory states or injecting messages (network, CAN, etc.).
6. Conclusion
Nowadays, there are many control units in new vehicles that operate switches and actuators based on sensor data. The amount of data flowing between these units is increasing, as well as the complexity of the methods.
Using Renode, virtual test cases can be created where corresponding tests can be assigned to virtual nodes connected through known communication channels (e.g., Ethernet, CAN, wifi, etc.). This makes prototype testing more flexible and accelerates the entire testing process. The benefits of simulation are evident as the complexity of automotive systems continues to rise, especially for new hardware components, where it must be determined whether new hardware components can fit into specific projects.
Renode is a relevant framework that supports automotive development, as it has test integration capabilities, an increasing hardware coverage (supporting different instruction set architectures), and automation possibilities. Further research should relate to SPICE-based circuit simulation.
(Translator’s note: This project is a research project of European universities, funded by the EU. If your company needs to carry out similar explorations, please feel free to contact us for more information; we offer virtual prototyping engineering implementation services based on commercial and open-source tools.)
Author Contributions
Conceptualization, F.S., D.F., and I.S.; methodology, I.S. and F.S.; validation, F.S.; investigation, I.S.; resources, I.S. and F.S.; writing—original draft preparation, F.S. and I.S.; writing—review and editing, F.S., D.F., and I.S. All authors have read and agreed to the published version of the manuscript.
Funding
This research was funded by the EU under the framework of the National Autonomous Systems Laboratory (RRF-2.3.1-21-2022-00002).
Institutional Review Board Statement
Not applicable.
Informed Consent Statement
Not applicable.
Data Availability Statement
The original data supporting the conclusions of this article will be made available by the authors upon request.
Conflicts of Interest
The authors declare no conflict of interest.
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