1. Layout

10 Rules for Component Layout:

1. Follow the principle of “large first, small later; difficult first, easy later,” meaning that important circuit units and core components should be prioritized in layout. 2. The layout should refer to the schematic diagram, arranging major components according to the main signal flow direction of the board. 3. The arrangement of components should facilitate debugging and maintenance, meaning that small components should not be placed around large components, and there should be enough space around components that require debugging. 4. For circuit sections with the same structure, adopt a “symmetrical” standard layout as much as possible; 5. Optimize the layout according to the standards of uniform distribution, center of gravity balance, and aesthetic appearance; 6. Components of the same type should be placed in the same direction along the X or Y axis. Similarly, polarized discrete components of the same type should strive to maintain consistency in the X or Y direction for ease of production and inspection. 7. Heating components should generally be evenly distributed to facilitate heat dissipation of the board and the entire machine; temperature-sensitive components, except for temperature detection components, should be kept away from high-heat components. 8. The layout should strive to meet the following requirements: keep total wiring as short as possible, with key signal lines being the shortest; completely separate high voltage and high current signals from low current and low voltage weak signals; separate analog signals from digital signals; separate high-frequency signals from low-frequency signals; ensure sufficient spacing for high-frequency components. 9. The layout of decoupling capacitors should be as close as possible to the IC’s power pins, forming the shortest loop with power and ground. 10. When laying out components, consider grouping devices that use the same power supply together for future power separation.

2. Routing

(1) Routing Priority

Key signal lines take priority: Analog small signals, high-speed signals, clock signals, and synchronous signals should be routed first. Density priority principle: Start routing from the most complexly connected components on the board. Begin routing from the area with the densest connections on the board. Points to note: a. Provide dedicated routing layers for clock signals, high-frequency signals, sensitive signals, etc., and ensure the minimum loop area. If necessary, manual routing, shielding, and increased safety spacing should be employed to ensure signal quality. b. The EMC environment between power and ground layers is poor, so avoid placing interference-sensitive signals. c. Networks with impedance control requirements should be routed according to line length and width requirements.

(2) Four Specific Routing Methods

1. Clock Routing:

The clock line is one of the factors that most affects EMC. Minimize vias on clock lines, avoid parallel routing with other signal lines, and keep them away from general signal lines to prevent interference. Also, avoid routing near the power section of the board to prevent interference between power and clock. If there is a dedicated clock generation chip on the board, no routing should be done beneath it; copper should be laid underneath, and ground should be cut if necessary. For many chips with reference crystal oscillators, no routing should be done beneath these oscillators; copper should be laid for isolation.

2. Right-Angle Routing:

Right-angle routing is generally to be avoided in PCB routing and has almost become a standard for measuring routing quality. So how much impact does right-angle routing have on signal transmission? Theoretically, right-angle routing causes changes in the transmission line width, resulting in impedance discontinuities. In fact, not only right-angle routing but also abrupt angles and sharp angles can cause impedance changes. The impact of right-angle routing on signals is mainly reflected in three aspects: first, corners can be equivalent to capacitive loads on the transmission line, slowing down the rise time; second, impedance discontinuities can cause signal reflections; third, sharp corners can generate EMI.

3. Differential Routing:

Refer to: Altium Designer — Differential Routing and Impedance Matching

Differential signals are increasingly used in high-speed circuit design, and the most critical signals in circuits often adopt differential structure design. Definition: Simply put, the driver sends two equal and opposite signals, and the receiver determines the logic state “0” or “1” by comparing the difference between these two voltages. The pair of traces carrying differential signals is called differential routing.

The most obvious advantages of differential signals compared to ordinary single-ended signals are reflected in the following three aspects: a. Strong anti-interference ability, as the coupling between the two differential traces is good; when external noise interference exists, it is almost simultaneously coupled to both traces, and the receiver only cares about the difference between the two signals, so external common-mode noise can be completely canceled. b. Effective suppression of EMI; similarly, due to the opposite polarities of the two signals, their electromagnetic fields radiated externally can cancel each other out, and the tighter the coupling, the less electromagnetic energy is radiated externally. c. Precise timing positioning; since the switching changes of differential signals occur at the intersection of the two signals, unlike ordinary single-ended signals that rely on high and low threshold voltages for judgment, they are less affected by process and temperature, reducing timing errors, and are also more suitable for low-amplitude signal circuits. The currently popular LVDS (low voltage differential signaling) refers to this small amplitude differential signal technology.

For PCB engineers, the most important concern is how to ensure that the advantages of differential routing are fully realized in actual routing. Anyone who has dealt with layout will understand the general requirements for differential routing, which are “equal length, equal spacing.” Equal length is to ensure that the two differential signals always maintain opposite polarities, reducing common-mode components; equal spacing is mainly to ensure that the differential impedance of both is consistent, reducing reflections. The “as close as possible principle” is sometimes also a requirement for differential routing.

4. Serpentine Routing:

Serpentine routing is a commonly used routing method in layout. Its main purpose is to adjust delay to meet system timing design requirements. Designers must first recognize that serpentine routing can degrade signal quality and alter transmission delays, so it should be avoided as much as possible during routing. However, in actual design, to ensure that signals have sufficient hold time or to reduce timing skew between signals in the same group, it is often necessary to deliberately route in a serpentine manner.

Points to note: Paired differential signal lines should generally be routed in parallel, minimizing vias; if vias are necessary, both lines should be routed through the same via to achieve impedance matching. Groups of signals with the same attributes should be routed side by side to maintain equal length as much as possible. Vias leading from surface mount pads should be kept as far from the pads as possible.

(3) Common Routing Rules

1. Direction Control Rules for Routing:

Adjacent layers’ routing directions should be orthogonal. Avoid routing different signal lines in the same direction on adjacent layers to reduce unnecessary inter-layer crosstalk; when this situation is unavoidable due to board structure limitations (such as certain backplanes), especially at higher signal rates, consider using ground planes to isolate each routing layer and ground signal lines to isolate each signal line.

2. Open Loop Check Rules for Routing:

Generally, dangling lines (Dangling Line) are not allowed, mainly to avoid the “antenna effect,” reducing unnecessary interference radiation and reception; otherwise, it may lead to unpredictable results.

3. Impedance Matching Check Rules:

The width of the routing for the same network should remain consistent; changes in line width can cause uneven characteristic impedance, leading to reflections at higher transmission speeds, which should be avoided in design. Under certain conditions, such as connector lead lines or BGA package lead lines with similar structures, changes in line width may be unavoidable, and the effective length of the inconsistent sections should be minimized.

4. Routing Length Control Rules:

That is, the short line rule; in design, the routing length should be kept as short as possible to reduce interference caused by excessive routing length, especially for important signal lines such as clock lines, which must have their oscillators placed very close to the devices. For situations where multiple devices are driven, the specific network topology structure should be determined based on the situation.

5. Chamfering Rules:

In PCB design, sharp angles and right angles should be avoided to prevent unnecessary radiation and poor process performance.

6. Decoupling Rules for Components:

A. Add necessary decoupling capacitors on the printed circuit board to filter out interference signals on the power supply, stabilizing the power supply signal. In multilayer boards, the position of decoupling capacitors is generally not too high, but for double-layer boards, the layout of decoupling capacitors and the routing of power will directly affect the stability of the entire system, sometimes even determining the success or failure of the design. B. In double-layer board design, the current should generally pass through filtering capacitors before being used by components. C. In high-speed circuit design, the correct use of decoupling capacitors is crucial for the stability of the entire board.

7. Component Layout Partitioning/Layering Rules:

A. Mainly to prevent mutual interference between modules operating at different frequencies while minimizing the routing length of high-frequency sections. B. For mixed circuits, analog and digital circuits can be arranged on opposite sides of the printed circuit board, using different layers for routing, with ground layers isolating them.

8. Ground Loop Rules:

The minimum loop rule states that the loop area formed by the signal line and its return path should be as small as possible; the smaller the loop area, the less radiation emitted externally and the less interference received from the outside.

9. Integrity Rules for Power and Ground Layers:

In areas with dense vias, avoid connecting vias in the power and ground layer’s hollow areas, which can disrupt the integrity of the plane layer and increase the loop area of signal lines in the ground layer.

10. 3W Rule:

To reduce crosstalk between lines, ensure that the spacing between lines is sufficient; when the center-to-center spacing of lines is at least three times the line width, 70% of the electric field will not interfere with each other, known as the 3W rule. To achieve 98% of the electric field not interfering with each other, a spacing of 10W should be used.

11. Shielding Protection:

Corresponding to the ground loop rules, this is also to minimize the signal loop area, commonly seen in important signals such as clock signals and synchronous signals; for particularly important signals with very high frequencies, consider using a copper shield cable structure design, isolating the routed line with ground on all sides, and also consider how to effectively connect the shield ground with the actual ground plane.

12. Termination Network Rules for Routing:

In high-speed digital circuits, when the delay time of PCB routing is greater than 1/4 of the signal rise time (or fall time), the routing can be considered a transmission line. To ensure that the input and output impedances match the transmission line impedance, various matching methods can be employed, depending on the network’s connection method and routing topology structure.

A. For point-to-point (one output corresponds to one input) connections, series matching at the start or parallel matching at the end can be chosen. The former has a simple structure and low cost but larger delay. The latter has better matching effects but is more complex and costly.B. For point-to-multipoint (one output corresponds to multiple outputs) connections, when the network topology is a daisy chain, terminal parallel matching should be chosen. When the network is star-shaped, point-to-point structure can be referenced. Star and daisy chain are two basic topological structures; other structures can be seen as deformations of the basic structure and can adopt flexible measures for matching. In practical operations, factors such as cost, power consumption, and performance should be considered; generally, complete matching is not pursued, as long as the reflections and other interferences caused by mismatches are kept within acceptable limits.

13. Loop Check Rules for Routing:

Prevent signal lines from forming self-loops between different layers. This issue is easy to occur in multilayer board designs, and self-loops can cause radiation interference.

14. Branch Length Control Rules for Routing:

Control the length of branches as much as possible; the general requirement isTdelay<=Trise/20.

15. Resonance Rules for Routing:

This mainly applies to high-frequency signal design, meaning that routing lengths should not be integer multiples of their wavelengths to avoid resonance phenomena.

16. Isolated Copper Area Control Rules:

The appearance of isolated copper areas can lead to unpredictable issues; therefore, connecting isolated copper areas with other signals helps improve signal quality, usually by grounding or removing the isolated copper area. In actual production, PCB manufacturers add copper foil to some vacant areas of the board, mainly to facilitate PCB processing and also to prevent warping of the printed circuit board.

17. Overlapping Power and Ground Layer Rules:

Different power layers should avoid overlapping in space. This is mainly to reduce interference between different power supplies, especially between power supplies with significant voltage differences. The issue of overlapping power planes must be avoided; if unavoidable, consider using an intermediate ground layer.

18. 20H Rule:

Due to the changing electric field between power and ground layers, electromagnetic interference radiates outward at the edges of the board, known as edge effects. The solution is to retract the power layer, ensuring that the electric field only conducts within the range of the ground layer. By retracting20H (the thickness of the dielectric between power and ground), 70% of the electric field can be confined within the edge of the ground layer; retracting100H can confine 98% of the electric field within.

(4) Others

For single and double-layer boards, power lines should be as thick and short as possible. The width requirements for power and ground lines can be calculated based on 1mm line width corresponding to a maximum of 1A current, and the loop formed by power and ground should be kept as small as possible.

To prevent coupling noise from entering load devices directly through long power lines, decoupling should be performed on the power supply before entering each device. To prevent mutual interference, each load’s power supply should be independently decoupled, ensuring filtering before entering the load.

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