Notes on Porting ZephyrRTOS to Sifli SF32LB58 - Part One

Adding SoC support for ZephyrRTOS (2) The basic framework for porting N32L406 is not yet complete, and recently I started the porting process for the Sifli SF32LB58. One reason is that this chip features Bluetooth and a 2D GPU, making it suitable for low-power display devices such as speedometers, navigation devices, and smart glasses, which I find quite interesting. Another reason is that the owner of Sifli is willing to support open source, stating that many chip register functionalities will be developed for the community, especially the Bluetooth interface, which they are willing to open up for the community to integrate with the ZephyrRTOS Bluetooth stack in the future. Therefore, I think it is worth trying. Additionally, they mentioned they are willing to provide some financial support to community developers, but based on the current discussions, I wouldn’t hold too high expectations for that.Let’s start with passion.All Sifli documentation can be downloaded from the official wiki: https://wiki.sifli.com/index.html.I started based on the official repository provided by https://github.com/OpenSiFli/zephyr, but due to code organization and dependencies, I reorganized and created a new repository:manifest repo: https://github.com/iotpi/sifli-porting-templatehal module: https://github.com/iotpi/hal_sifli, which mainly contains the baremetal drivers for the chip.zephyr porting: https://github.com/iotpi/sifli_zephyr, this repository is expected to eventually merge into the Zephyr upstream, but the workload is still enormous and seems far away Notes on Porting ZephyrRTOS to Sifli SF32LB58 - Part One Additionally, a friend has continued to modify the organizational structure based entirely on the official repository, which is located in his own repository: https://github.com/ck-telecom/zephyr-SiFli, interested friends can also take a look.1. Chip ArchitectureThis chip architecture is somewhat complex, with three cores: HCPU, ACPU, and LCPU. The LCPU is generally used to run the Bluetooth protocol stack. The Bluetooth protocol stack is still closed source. Here, the HCPU and ACPU together form the HPSYS, while the LCPU forms the LPSYS.2. Device Tree (devicetree, dts)I looked at the DTS definitions for multi-core MCU architectures from NXP and Nordic, which define all cores in a base dtsi file and then remove specific nodes in the dtsi definitions for particular cores using /delete-node/. I currently do not understand why they use this method, and even asked Zephyr experts, who were also uncertain. Therefore, I have organized it in a way that I believe is more suitable, and if I encounter new issues later, I will consider modifying this structure. Based on the chip functional block diagram above, I defined the basic dts files:sf32lb58.dtsi, used to define peripherals shared by the entire SoC;sf32lb58_hpsys.dtsi, defines peripherals (memory) shared by HCPU and ACPU;sf32lb58_hcpu.dtsi, accessible CPU and memory only for HCPU;sf32lb58_acpu.dtsi, accessible CPU and memory only for ACPU;sf32lb58_lpsys.dtsi, defines devices and memory accessible by LPSYS;sf32lb58_lcpu.dtsi, defines CPU and memory related to LCPU.sf32lb586.dtsi: defines specific configurations for sf32lb586, mainly for the combined PSRAM and FLASH configurations.sf32lb586_hcpu.dtsi: this file should include the header files defined by the board-level dtsSimilarly, sf32lb586_acpu.dtsi and sf32lb586_lcpu.dtsi also need to be defined.Note that the screenshots above are for reference only; the final compilation may have issues or other architectural reasons, and the above content may still change.Stay tuned for the next installment.If there are any errors in the article, or if you have any suggestions, feel free to leave a comment! Thank you!