Recently, MediaTek announced a significant milestone: their first flagship chip based on TSMC’s 2nm process has completed tape-out. In simple terms, this means the chip design is finished, and it is now entering the “real-world testing” phase—specifically, the manufacturing verification stage. More importantly, they stated: this chip is planned to enter mass production by the end of next year.
The significance of this event is substantial. First, it is essential to understand the implications of the 2nm process. The smaller the nanometer number, the denser the transistors, allowing for more functions to be packed into a given area, resulting in stronger computing power and higher energy efficiency. This is foundational support for our key developments in AI computing power, edge computing, 5G communication, and even automotive-grade chips.
TSMC’s 2nm process utilizes “nanosheet transistor” technology, which is a new generation of transistor architecture following FinFET transistors. This is akin to upgrading a building from 6 stories to 60 stories, accommodating more “people” while consuming less energy. According to TSMC’s data, this new process improves logic density by 1.2 times compared to the current 3nm N3E process, with performance increasing by 18% at the same power consumption. If you want to save energy, it can also reduce power consumption by 36% at the same performance level. For smartphones, this translates to longer battery life, less heat generation, and significantly enhanced performance.
From a global perspective, TSMC remains the “king” of the wafer manufacturing industry, especially in advanced processes. Major companies like Apple, NVIDIA, MediaTek, and Qualcomm are all reliant on it. Take Apple, for instance; the A-series processors almost annually utilize TSMC’s latest processes, which has become a core advantage for iPhones over Android devices.
However, not everyone can access 2nm technology. Firstly, the costs are high. Industry estimates suggest that a single 2nm wafer could cost as much as $30,000, not including subsequent packaging, testing, yield loss, and other processes. When all is accounted for, the manufacturing cost of a flagship SoC could double. Secondly, there are capacity limitations. Although TSMC plans to build four 2nm factories by 2026 with an annual output of 60,000 wafers, this is still far from sufficient to meet global demand.
For us, it is unlikely to achieve 2nm mass production in the short term, whether it be manufacturing equipment, photolithography machines, or EDA design tools, we are still constrained. But this does not mean we are powerless.
Firstly, China already possesses considerable capabilities in “chip design.” For example, Huawei’s Kirin 9000S, although the process has not been explicitly disclosed, is widely believed to use SMIC’s 7nm technology. While its performance may not match Qualcomm’s, it is still competitive. More importantly, MediaTek is itself a Taiwanese company, yet it holds the largest market share in the global SoC market at 36%, surpassing Qualcomm. A significant portion of MediaTek’s products are sold in the Chinese market, meaning our consumption capacity in the downstream market also supports their investment in advanced technology research and development.
Secondly, China is actively laying out alternative routes. Companies like Changxin in Hefei have made breakthroughs in DRAM, and Yangtze Memory Technologies in Wuhan has made strides in NAND Flash; SMIC maintains stable production capacity in mature processes of 14nm and 12nm while transitioning to 7nm and even 5nm. Domestic EDA vendors are also gradually overcoming challenges in the basic toolchain. All of these efforts represent “accumulating strength for a leap forward,” and once the timing is right, a window for leapfrog development will open.
Another trend that cannot be overlooked is the impact of AI on the technological direction of the chip industry. In the past, chips primarily pursued general computing power, but now AI, especially edge AI, demands heterogeneous computing and dedicated chips, such as NPU and ASIC, which provide China’s semiconductor industry with the possibility of “taking a shortcut.” Companies like Cambricon and Horizon Robotics are navigating this track; although their current scale is limited, once applications are implemented (such as autonomous driving, smart cities, and industrial control), demand will explode.
Returning to MediaTek’s successful 2nm tape-out, this is not only a technological breakthrough for TSMC but also a significant market strategy move. It signifies that the next round of competition in smart devices will enter a new phase of “hardware dividends”: whoever masters stronger AI computing power and better energy efficiency will capture user mindshare. And this foundational core is the chip.
Therefore, we must pay attention to the movements of international giants while also being clear about our position: do not blindly follow trends, but do not remain stagnant either. Future competition will be an ecological-level contest; for Chinese chips to rise, it will rely not only on technological breakthroughs but also on collaborative innovation across the entire chain and policy guidance.
Disclaimer: Some sentences in this article have been polished with AI assistance, and all content has undergone strict review and verification. The article advocates positive energy and avoids vulgarity and negative guidance.
2025-09-22 Sina Finance: 2nm, the battle begins
2025-09-16 Sina Finance:MediaTek’s first TSMC 2nm flagship SoC completes tape-out, expected to enter mass production by the end of 2026