Mastering SPI Communication: Comprehensive Guide to Four-Wire and Seven-Wire Applications

1. Overview of SPI Communication

SPI (Serial Peripheral Interface) is a synchronous serial communication protocol developed by Motorola (now NXP), primarily used for short-distance, high-speed communication between master and slave devices. Its features include full-duplex transmission, master-slave architecture, and no complex protocol layers, making it widely used in embedded devices such as memory (e.g., Flash), sensors, and displays. Compared to I2C, SPI is faster and has no address conflicts, but requires more hardware connections.

2. Principles of SPI Communication

SPI is based on the master-slave mode, where the master device controls the clock signal (SCLK) and initiates data transmission, while the slave device responds. The core signal lines include:

1. SCLK (Serial Clock): The clock signal output by the master device, synchronizing data transmission.

2. MOSI (Master Out Slave In): The line for the master device to send data to the slave device.

3. MISO (Master In Slave Out): The line for the slave device to send data to the master device.

4. SS/CS (Slave Select/Chip Select): The master device pulls this line low to select the target slave device.

3. Four-Wire SPI (Standard Mode)

Four-wire SPI is the standard configuration, consisting of the four signal lines mentioned above (SCLK, MOSI, MISO, SS). Its workflow is as follows:

1. Initialization: The master device configures the clock polarity (CPOL) and phase (CPHA), determining the data transmission edge.

2. Chip Select Activation: The master device pulls the SS line of the target slave device low to initiate communication.

3. Data Transmission: During each clock cycle, the master and slave devices exchange 1 bit of data simultaneously via MOSI and MISO, achieving full-duplex communication.

4. Multiple Slave Connections: Each slave requires an independent SS line. The master device selects the communication target by controlling different SS lines.

Master Device         Slave Device 1         Slave Device 2SCLK  ──────┬───── SCLK ──── SCLKMOSI  ──────┼───── MOSI ──── MOSIMISO  ──────┼───── MISO ──── MISOSS1   ──────┤     (SS1 low level selected)SS2   ─────────────┤     (SS2 low level selected)

Clock Modes: SPI supports four clock modes, determined by the combination of CPOL and CPHA:

• Mode 0 (CPOL=0, CPHA=0): Clock idle low, data sampled on the rising edge.

• Mode 1 (CPOL=0, CPHA=1): Clock idle low, data sampled on the falling edge.

• Mode 2 (CPOL=1, CPHA=0): Clock idle high, data sampled on the falling edge.

• Mode 3 (CPOL=1, CPHA=1): Clock idle high, data sampled on the rising edge.

4. Variants of SPI with Extended Lines

1. Three-Wire SPI (Half-Duplex)

By multiplexing MOSI and MISO into a single data line (SISO), half-duplex communication is achieved. The master and slave devices transmit data in a time-sharing manner, suitable for scenarios with limited pin resources, but sacrificing transmission speed.

2. Two-Wire SPI (Simplified Mode)

Some devices omit the MISO line, supporting only unidirectional transmission from master to slave (e.g., configuration-only read sensors), but this mode is less common.

3. Seven-Wire SPI

Seven-wire is not a standard SPI protocol but an extended configuration for specific scenarios, commonly found in the following two cases:

• Quad SPI (QSPI): Uses 4 data lines (IO0-IO3) to increase throughput, transmitting 4 bits of data per clock cycle. The signal lines include:

• SCLK, CS (2 lines)

• IO0-IO3 (4 lines)

• Optional additional WP (Write Protect) and HOLD (Pause) lines (totaling 7 lines). This configuration is common in high-capacity Flash memory (e.g., W25Q128JV), supporting high-speed read and write operations.

Master Device          Flash MemorySCLK  ─────── SCLKCS    ─────── CSIO0   ─────── IO0 (Data Line 1)IO1   ─────── IO1 (Data Line 2)IO2   ─────── IO2 (Data Line 3/WP)IO3   ─────── IO3 (Data Line 4/HOLD)WP    ─────── WP (Optional)HOLD  ─────── HOLD (Optional)

• Device-Specific Control Lines: Some slave devices require additional functional lines, such as:

• INT (Interrupt Request): Notifies the master device that data is ready.

• RESET: Hardware reset signal.

• READY: Indicates the status of the slave device. These extended lines need to be connected according to the specific device manual.

5. SPI Extended Modes: Dual and Quad

1. Dual SPI: Uses MOSI and MISO to transmit data simultaneously (2 bits per cycle), increasing speed, suitable for scenarios like LCD controllers.

2. Quad SPI: Achieves 4 bits of transmission per cycle through 4 data lines (IO0-IO3), with speeds up to 4 times that of standard SPI, requiring both master and slave devices to support this mode.

6. Application Scenarios and Advantages/Disadvantages

Applications:

• Memory: SPI Flash (e.g., W25Q series).

• Sensors: Temperature sensors (e.g., MAX31865), IMUs (e.g., MPU6050).

• Displays: OLED drivers (SSD1306).

Advantages:

• High-speed full-duplex transmission (up to 100 Mbps).

• Simple hardware implementation, with no complex protocols.

Disadvantages:

• No flow control or acknowledgment mechanism; reliability depends on hardware design.

• Multiple slaves require many SS lines, consuming master device IO resources.

7. Conclusion

The standard four-wire SPI has become mainstream in embedded communication due to its efficiency and simplicity, while variants like seven-wire meet specific needs (e.g., QSPI) by extending data lines or control signals. When designing, it is essential to determine the wiring and mode based on the device manual, balancing speed, pin resources, and system complexity.

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