EMB(External Memory Bus)

-> Supports 16-bit data width

-> Supports synchronous or asynchronous timing mode control

-> Allows CPU code to run on external SRAM

-> Supports data reception and transmission using DMA buffering

-> Configurable timing cycle for address latch time and data access time

-> Supports SRAM, NOR/NAND-flash, LCD interface

CRC(Cyclic Redundancy Check)

-> CRC hardware engine

-> Supports 4 types of polynomials

CRC8 polynomial 0x07

CRC16 polynomial 0x8005

CRC-CCITT16 polynomial 0x1021

CRC32 polynomial 0x4C11DB7

-> Programmable CRC initial value

-> DMA data transfer supports CRC

DAC(Digital-to-Analog Converter)

-> One 10-bit current-type DAC

Maximum conversion rate of 100KHz

Can simulate output to ADC internal channel

-> Can start conversion via writing registers, external pins, and internal events

-> Programmable full-scale output current (0.5/1/2 mA)

-> Input data can be left/right aligned

Configurable data width: 10/8 bits

-> Supports DMA

DMA(Direct Memory Access)

->3 independently configurable hardware DMA channels

Memory, APB, and AHB peripherals can be accessed as source or destination

Memory includes SRAM and EMB access memory space

Peripherals include ADC0, DAC, I2Cx, URTx, SPIx, TM36, and GPL modules

-> DMA transfer management types

Memory-to-Memory

Peripheral-to-Memory

Memory-to-Peripheral

Peripheral-to-Peripheral

I2C Wake-up Function