Summary1. Introduction to ARM Cortex-M7 Core2. High Performance Implementation of ARM Cortex-M7 Core2.1 Dual Issue 6-stage Instruction Pipeline with Branch Prediction2.2 Instruction Set Extension (ISA) vs. Dual Issue2.3 Tight Coupled Memory (TCM)2.4 Dedicated DMA Access Interface for TCM (AHBS)2.5 Cache2.6 High Performance Peripheral Interface (AHBP)2.7 High Performance Internal Bus Interconnect Matrix (AXIM)Conclusion1. Introduction to ARM Cortex-M7 CoreThe ARM Cortex-M7 core, or CM7, codenamed “Pelican”, is a large-bodied water bird, about 1.7 meters long with a wingspan of up to 3 meters. Its strong wings can easily lift its massive body into the sky. Weighing up to 13 kilograms, it is one of the largest birds in existence.
The ARM Cortex-M7 core is named to declare its high-performance CPU core supremacy in the embedded MCU application field.The ARM Cortex-M7 core is currently the highest performance core in the ARM Cortex-M series, achieving up to 2.14 DMIPS/MHz and 5.01 CoreMark/MHz performance, optimized for advanced processes like 40nm (40LP), 28nm (28HT), and 16nm (16FFC). It can achieve high performance (1.4GHz @ 16FFC) while also achieving lower power consumption (18.5uW/MHz @ 16FFC), allowing for reduced size and lower hardware implementation costs.
Next, this article will take you through the high performance of the ARM Cortex-M7 core, especially how the Dual Issue ISA is implemented.2. High Performance Implementation of ARM Cortex-M7 Core2.1 Dual Issue 6-stage Instruction Pipeline with Branch PredictionThe ARM Cortex-M7 core employs a Dual Issue 6-stage instruction pipeline design with branch prediction, combined with high-performance, low-latency (zero access wait cycles) on-chip tightly coupled memory (I-TCM & D-TCM) and instruction and data cache (I-Cache & D-Cache), ensuring that most instructions can be executed in parallel.
Specifically, the 6-stage instruction pipeline of the ARM Cortex-M7 core is implemented such that each instruction is processed by the same fetch and decode pipeline units in the first two stages, with instruction dispatch (issue) occurring in the third stage, identifying its instruction type (memory access [load/store pipeline], arithmetic logic operation [ALU pipeline], multiply-accumulate operation [MAC pipeline], floating-point operation [FPU pipeline]), allowing for parallel execution of different instructions.
Among them, the ARM Cortex-M7 core implements two shifters and ALUs, having two ALU pipelines, ensuring that commonly used integer processing instructions can also be processed in parallel, greatly enhancing the computational performance of the CPU core.
2.2 Instruction Set Extension (ISA) vs. Dual IssueIn terms of instructions, the ARM Cortex-M7 core, as the highest-end core of the ARMv7-M architecture, has extended its integer instruction set, DSP instruction set, and floating-point instruction set compared to previous Cortex-M0/M+ and Cortex-M3/4 cores, supporting multi-core exclusive access, dual-word (dual-word, 64-bit) memory read/write access (STRD, LDRD), more powerful DSP instructions, and double-precision floating-point processing (double FPU):
Some limitations of the ARM Cortex-M7 core’s dual-issue pipeline include:① An additional instruction cycle is needed for address-based pointer access load operations;② Two FPU, SIMD, and MAC instructions cannot be issued simultaneously because the corresponding FPU, MAC, and SIMD-supporting ALU hardware is limited to one;
③ Multi-byte and double-word load and store instructions, exclusive access instructions, unaligned load and store instructions, integer and floating-point division instructions, floating-point square root instructions, all double-precision floating-point instructions, and special kernel instructions (e.g., SVC instructions and breakpoint instructions BKPT that trigger kernel exceptions on the same call) cannot be executed in parallel with any other instructions;
④ Dual issue memory access, storing data in different D-TCM ports with 32-bit/16-bit/8-bit data access can also support dual issue parallel execution, but accessing system memory (SRAM and Flash) through D-Cache does not support dual issue;
To complement the dual-issue instruction pipeline and ensure core performance, the ARM Cortex-M7 core is also equipped with a dedicated tightly coupled memory interface (TCM interface), providing 64-bit wide instruction tightly coupled memory (64-bit I-TCM) and two 32-bit wide data tightly coupled memory (Dual 32-bit I-TCM) expansion interfaces; and a high-performance bus interface (AXI master) with instruction and data cache (I/D-Cache) functionality as access interfaces for system memory (SRAM & Flash):
2.3 Tight Coupled Memory (TCM)Tight Coupled Memory (TCM) is a key configuration for the ARM Cortex-M7 core to achieve high performance. Through a dedicated tightly coupled memory interface, it can support a maximum of 16MB of I-TCM and 16MB of D-TCM, and is equipped with a dedicated high-speed DMA access interface (AHBS):
I-TCM: Used for storing code, with a 64-bit data width;
D-TCM: Used for storing data, with dual-port 64-bit data width;
I-TCM and D-TCM use independent bus Harvard architecture design, and access does not go through the chip’s system bus matrix (AXI, or CrossBar), providing zero wait cycles, thus ensuring high-speed operation of the core.
In addition, I-TCM and D-TCM also support ECC error correction and detection, ensuring the reliability of code and data storage, meeting functional safety requirements.
2.4 Dedicated DMA Access Interface for TCM (AHBS)The ARM Cortex-M7 core supports DMA access to data in TCM through a dedicated AHBS interface, allowing results processed by the core in TCM to be moved by DMA to peripherals for transmission (e.g., CAN-FD, FlexRay, Ethernet, etc.), and data received by peripherals can also be moved to TCM using DMA, greatly improving the data processing bandwidth of the MCU/SOC system while reducing CPU loading.
Tips: It is worth noting that when DMA accesses TCM via the AHBS interface, it needs to use the backdoor access address of TCM, for example, the backdoor access address mapping of the I-TCM and D-TCM of the NXP S32K3 series MCU is as follows:
2.5 CacheTo ensure the core’s performance when using low-speed memory like SRAM and Flash, the ARM Cortex-M7 is equipped with 4~64KB of instruction and data cache (I&D-Cache), reducing the number of times the core accesses SRAM and Flash through the system bus matrix.Independent I-Cache and D-Cache, Harvard architecture design, ensure that instruction fetching can read and write data simultaneously;I-Cache and D-Cache are disabled by default and must be enabled before use (usually done in the MCU/SOC startup code);
The Cache of the ARM Cortex-M7 core supports ECC error correction and detection:
D-Cache: Single-bit correction, multi-bit detection (SEC-DED ECC32, 32-bit user data + 7 bit ECC check);
I-Cache: Single-bit correction, multi-bit detection (SEC-DED ECC64, 64-bit user data + 8 bit ECC check);
2.6 High Performance Peripheral Interface (AHBP)The ARM Cortex-M7 core also reserves a 32-bit AHBP interface for high-performance low-latency peripheral connections: peripherals expanded through this interface do not need to go through the system bus interconnect matrix during read/write access, thus ensuring high performance and low latency.
2.7 High Performance Internal Bus Interconnect Matrix (AXIM)The ARM Cortex-M7 core is equipped with the ARM 4th generation AMBA bus matrix – AXIM, providing the MCU/SOC with 64-bit memory and peripheral bus interconnect capabilities. When accessing memory (SRAM and Flash) and peripherals through AXIM, the kernel’s MPU can be configured to enable I-Cache and D-Cache, thus accelerating access and further improving system efficiency.
ConclusionThe following is a comparison and summary of the access latency of various memory and peripheral interfaces of the ARM Cortex-M7 core introduced in this article: TCM and cache hit (Cache Hit) AXI access both have zero wait cycles, while AHBP interface access latency is fixed at 2 cycles, and for cache miss and non-cacheable AXI memory access as well as peripherals through AXI, the latency is 4 wait cycles:
That concludes what I wanted to share with you today about the key configurations for achieving high performance in the ARM Cortex-M7 core. Since its introduction around 2010, many semiconductor companies have launched high-performance MCUs/MPUs based on the ARM Cortex-M7 core, such as ST’s STM32F7 and STM32H7 series high-performance general-purpose MCUs:
NXP’s i.MX RT series crossover MCU and S32K3 series high-performance general-purpose automotive MCUs:
In the future, I will introduce the specific TCM and Cache configurations and usage methods based on the specific NXP S32K3xx series high-performance automotive general-purpose MCU and their impact on performance, so stay tuned.
That’s all I wanted to share with you today. I hope it helps and inspires you.
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