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The timer instruction is a very common type of instruction in PLC program design, and the timer instruction format and usage of the S7-1200 series PLC are different from those of the S7-200 series PLC.
The S7-1200 series PLC uses IEC standard timer instructions, and the number of timers that can be used in user programs is only limited by the CPU memory capacity. Each timer uses a 16-byte IEC_TIMER data type DB structure to store the timer data specified by the functional block or coil instruction at the top, as shown in the figure below.
There are several types of timers in the S7-1200 series PLC, including pulse timers, on-delay timers, off-delay timers, and retentive on-delay timers.
1. Pulse Timer
The pulse timer instruction is identified as TP, and this instruction is used to generate a pulse with a preset width of time. The IN terminal of the timer instruction is used to enable the timer, the PT terminal indicates the preset value of the timer, Q indicates the output state of the timer, and ET indicates the current value of the timer. The instruction format and timing diagram of the pulse timer instruction are shown in the figure below.
Using the TP instruction, the output Q can be set for a preset period of time. When the state of the timer’s enable terminal changes from OFF to ON, the timer instruction can be activated and starts timing. Regardless of any subsequent changes in the state of the enable terminal, the output Q will remain set for the duration specified by PT. If the timer is timing, even if the signal indicating the enable terminal changes from OFF to ON during this time, the output Q’s signal state will not be affected.
Based on the timing diagram of the pulse timer, the following program execution process can be analyzed.
When I0.5 is ON, the state of Q0.4 is ON, and after 5S, the state of Q0.4 changes to OFF. During this 5S period, regardless of how the state of I0.5 changes, the state of Q0.4 remains ON.
2. On-Delay Timer
The identifier for the on-delay timer is TON. The output Q of the on-delay timer will be ON after the preset delay time has elapsed. The pin definitions in the instruction are consistent with those of the TP timer instruction. The program shown below describes the instruction format and execution timing diagram of the on-delay timer.
When the enable terminal of the timer is 1, this instruction is activated. Once the timer instruction is activated, it starts timing. When the current value ET of the timer equals the preset value PT, the output Q will be ON. As long as the state of the enable terminal remains ON, the output Q will continue to be ON. If the state of the enable terminal changes to OFF, the output Q will be reset to OFF. When the enable terminal is ON again, the timer function will restart.
Based on the execution timing diagram of the on-delay timer, the meaning and execution process of the program shown in the following figure can be analyzed.
This program mainly completes the function of starting the output and then automatically disconnecting after a delay: when I0.5 is ON, it executes the set function in the reset priority instruction, making Q0.4 output ON. When Q0.4 output is ON, it activates the on-delay timer TON, causing the timer to work and delay. After a 10S delay, the output Q of the timer will be ON, and at this time, the reset signal in the reset priority instruction will be ON, thus executing the reset function, so Q0.4 output remains ON.
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