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Since the RISC-V instruction set architecture was born at the University of California, Berkeley in 2010, this open-source architecture has undergone over a decade of development. From its initial academic research and open-source experiments to the establishment of the RISC-V Foundation in 2015, marking the acceleration of industrialization, and the foundation’s relocation to Switzerland in 2020 to address geopolitical risks, RISC-V has gradually built a global open-source ecosystem.
Today, the RISC-V open-source ecosystem is entering a new phase of breakthroughs in key areas such as IoT, high-performance computing, and AI. Recent developments show that RISC-V is not only rapidly gaining popularity in edge devices but is also beginning to shine in high-end application scenarios such as server chips and autonomous driving, with its open and modular characteristics continuously attracting global developers to join this wave of transformation.
To further understand the key nodes and latest developments in the RISC-V open-source ecosystem, a reporter from Weixin Network interviewed Tang Dan, the director of the Beijing Open Source Chip Research Institute, at the 2025 RISC-V China Summit.
Classic Works of RISC-V Open Source IP
Every industry’s leap is built on the shoulders of classic cases—they are both beacons of experience and springboards for innovation, enabling successors to continuously break through ceilings. So, which processor IPs can be considered classic cases of RISC-V?
Tang Dan’s answer is: Rocket-chip, Hummingbird, and XuanTie. Why these three processor cores?
Tang Dan explained: “Berkeley’s Rocket-chip was the first stop for many people to get in touch with RISC-V. Ten years ago, this single-issue core capable of running Linux was remarkably efficient in terms of power consumption and area, and even though its specifications may seem modest today, it was a rarity back then.”
He then turned his attention to domestic development: “In China, many people learned RISC-V starting from Hu Zhenbo’s ‘Hands-on Guide to CPU Design.’ The Hummingbird core developed by his team targets the IoT field and is more like a streamlined MCU, opening the door to RISC-V for domestic developers.”
“The key step that truly pushed RISC-V towards industrialization,” Tang Dan emphasized, “was the release of the commercial-grade open-source XuanTie cores, such as C906/C908/C910, by Pingtouge in 2021. This is regarded as an important milestone in the history of RISC-V open source. Nowadays, companies venturing into the RISC-V field often list these three IPs as their preferred options.”
At the same time, Tang Dan hopes that ‘Xiangshan’ can also join the ranks of RISC-V classics. He said: “‘Xiangshan’ is already a commercial-grade, high-performance open-source core. In desktop/server scenarios, its PPA (Performance, Power, Area) is competitive with CPUs based on the Arm architecture, and may even surpass it. What’s more, the Open Chip Institute has not only open-sourced all RTL but also made the design process, verification tools, SoC integration, and lock-step technology public—this is top-level confidential information in any company. Currently, the first batch of users has already begun mass production of chips based on ‘Xiangshan,’ and it has every chance of becoming the next milestone for RISC-V.”
It is reported that many companies in the market are already using RISC-V open-source IP for chip development, mainly focusing on mainstream open-source cores like Rocket-chip, Pulpino, and Hummingbird. The high-performance ‘Xiangshan’ processor will also gradually enter the commercial stage this year. However, in terms of mass production scale, commercial IP still dominates.
In this regard, Tang Dan stated: “Although open-source IP has the advantages of no licensing fees and immediate usability, especially suitable for research institutions, schools, and pre-research projects in enterprises, commercial IP, with its mature after-sales support system and prices now dropping to tens of thousands, is more attractive for mass production projects.”
RISC-V is Racing at Twice the Speed of Arm
According to the latest forecast from industry analysis firm SHD Group, the global RISC-V market is expected to reach $92.7 billion by 2030, with an average annual compound growth rate of 47.4%, demonstrating strong development momentum. This growth expectation aligns with the RISC-V Foundation’s judgment, which predicts that from 2021 to 2027, the shipment volume of RISC-V cores in the Chinese market will account for half of the global total.
In this regard, Tang Dan shared a statistic from the industry: RISC-V will develop at twice the speed of Arm to reach Arm’s current level, because the open ecosystem develops faster.
He explained: “In the traditional model, commercial instruction sets used by high-performance processor cores are strictly controlled by companies. For example, the core code of SPEC CPU2006 single-threaded 15 points/GHz is considered confidential technology in various companies. RISC-V breaks this convention, just like the Open Chip Institute’s ‘Xiangshan’ high-performance processor achieves complete open-source. This transformation is reminiscent of the Linux revolution twenty years ago: before Linux appeared, the Unix operating system was only accessible to a few; after Linux was widely adopted in the industry, it became a fertile ground for academic innovation, which in turn quickly fed back into the industry, forming a positive cycle.”
Although some companies still view RISC-V as another Arm, Tang Dan pointed out that only by fully leveraging the open-source characteristics can RISC-V’s potential be truly unleashed. For example, if the ‘Xiangshan’ high-performance processor achieves 15 points/GHz performance (note: Apple’s M series processors achieve 22 points/GHz), it means that the performance benchmark for global RISC-V processor cores will be raised overall. This is the core value of the open-source ecosystem—avoiding redundant investments, sharing and reusing innovative results, thus accelerating the technological evolution of the entire industry.
It is worth mentioning that the migration time from Arm architecture to RISC-V is shortening. Tang Dan believes that current MCU memory resources are no longer so tight. In the case of using C language, as long as the initialization is done and the stack is set up, more than half of the migration work is completed, so in a fast scenario, migration can be completed in a day.
Overall, whether open-source or commercial RISC-V processors, the overall technical level is already quite close, continuously narrowing the performance gap with traditional Arm architectures. This parallel development trend marks that the RISC-V ecosystem has entered a new stage of high-quality development.
Open Source Progress: Open Source IP > Open Source EDA > Open Source PDK
The three key elements of the open-source chip technology system are “open-source IP, open-source EDA, and open-source PDK.” What is the current development status of RISC-V in these three areas?
In this regard, Tang Dan told Weixin Network: “In terms of open-source IP, there are many open-source IPs available across low-end, mid-range, and high-end, and they can basically reach a commercial level.”
“In terms of open-source EDA, it currently only supports processes above 28nm, as the positioning of open-source EDA is not aimed at advanced processes for high-performance chips. Open-source in high-end fields is still quite challenging. Currently, the ‘iEDA’ toolchain, developed by Professor Bao Yungang’s team at the Institute of Computing Technology, Chinese Academy of Sciences, is the first open-source EDA (Electronic Design Automation) toolset in China that supports 28nm processes, and its feasibility has been verified in RISC-V chips (such as ‘Xiangshan’). EDA and PDK are bound together.”
“In terms of open-source PDK, there will be some breakthroughs this year or next year. Currently, the French semiconductor research institution CEA-Leti has released a 0.18μm open-source PDK, and the American SkyWater Technology is the world’s first foundry to provide a completely open-source PDK, supporting 0.13μm CMOS technology (SKY130). In contrast, domestic open-source PDK may be able to support 65nm processes right from the start, which may be faster.”
Regarding open-source PDK, Tang Dan further revealed: “Open-source PDK is not a technical issue but a commercial issue, involving whether foundries are willing to disclose their intellectual property. This is quite challenging. However, we understand that there are companies in the industry working on this, and there may be significant breakthroughs this year or next year.”
It is worth mentioning that during the 2025 RISC-V China Summit, several local EDA companies announced their joint testing and verification results with the Open Chip Institute’s ‘Xiangshan’ series processors, stating that ‘Xiangshan’s’ open-source nature has a strong driving effect on domestic EDA. So, what exactly does this driving effect manifest in?
In this regard, Tang Dan stated: “In complex chip design, the verification workload accounts for more than 70%. For large-scale RISC-V chips, verification coverage and efficiency also face significant challenges. Taking ‘Xiangshan’ as an example, we collaborate with domestic EDA companies to verify their tools while also verifying our IP. Currently, it is difficult for EDA companies to find commercial users to try out new tools, as everyone is reluctant to take on such risks. Therefore, the scale of open-source ‘Xiangshan’ is a great choice that can meet their extreme testing needs. Additionally, even if they find commercial customers to collaborate on testing, due to confidentiality requirements regarding intellectual property, EDA companies cannot showcase successful cases as examples to other companies, but testing based on ‘Xiangshan’ can. Therefore, many domestic EDA companies actively approached the Open Chip Institute to arrange machines and professionals for on-site testing and publicly share the results to demonstrate the usability and value of their tools.”
However, when asked whether the Open Chip Institute would collaborate with domestic EDA companies to promote the ‘One Chip for All’ open verification platform, Tang Dan clarified: “‘Xiangshan’ uses commercial EDA tools, while the ‘One Chip for All’ platform mainly uses open-source tools, which are open to students worldwide, so the threshold must be low enough. First, we need to provide a set of open, free, and open-source tools that can support processes of 28nm and above. Commercial EDA software is not the optimal choice, so we will not embed our partners’ commercial EDA software in it for now.”
The Eve of RISC-V’s High-End Market Explosion in 2025
Currently, the trend of RISC-V’s high-end development is very strong and has become the focus of global summits. Its two main lines of high-end development are: one is general computing power, covering traditional scenarios such as servers and PCs; the other is AI computing power, targeting cutting-edge areas such as AI servers, autonomous driving, and AI PCs.
In this regard, Tang Dan predicts: 2025 will be the “dawn” of RISC-V high-end applications, and 2026 will see a large-scale explosion of servers, desktops, and terminals.
It is reported that the global high-end RISC-V processor camp has already taken shape: internationally, products like SiFive P870, Ventana Veyron V1/Veyron V2, and Tenstorrent Ascalon are leading the way, while each year new startups targeting the high-end market emerge at the European summit; domestically, XuanTie and ‘Xiangshan’ represent the forefront, along with some self-developed projects from various companies, collectively driving technological development.
According to public information, in February of this year, ‘Xiangshan’ successfully adapted and locally deployed the DeepSeek-R1-Distill-Qwen-1.5B large model. Additionally, companies like Moore Threads, Tencent, and Sunnan are developing high-end chips such as AI chips, server chips, and GPUs based on ‘Xiangshan.’
Moreover, fragmentation has been the most discussed issue in RISC-V discussions over the past few years, but in the high-end field, this problem is gradually being resolved through standardization efforts.
By the end of 2024, the RISC-V International Foundation proposed RVA23 (RISC-V Application Profiles), clearly dividing instruction set extensions in the high-end market into mandatory and optional categories, such as the server profile requiring support for V extensions and multi-core consistency (SMP); edge computing profile allowing for optional floating-point units (F/D extensions not mandatory), thus forcing convergence to address the fragmentation caused by the unordered expansion of the RISC-V instruction set.
As a result, if hardware manufacturers claim their products are compatible with the RVA23 server specification, they must implement the basic instruction set; otherwise, they cannot pass certification, and the software ecosystem only needs to develop according to the specifications.
It is reported that many leading chip manufacturers globally have fully supported RVA23 in their high-end RISC-V products, such as the aforementioned Ventana Veyron V1/Veyron V2 and Tenstorrent Ascalon.
What is the “Killer Application” that Will Ignite the RISC-V Industry?
When a new instruction set emerges, it often first succeeds in emerging industries, establishing a foothold before expanding into others. However, an instruction set can only form a good ecosystem if it succeeds in high-end fields.
The starting point for the success of the x86 ecosystem was not in the high-end market; at that time, the high-end market was dominated by IBM and HP’s mainframe market, while Intel started in the PC market, achieving success before moving into servers and gradually replacing the mainframe market.
Similarly, the logic behind Arm’s growth is the same. Looking back at Arm’s rise, it is clear that it did not start in the high-end. For over twenty years after its birth in 1985, Arm focused on low-power, low-cost embedded MCUs, with the most active cores in the market around 2009 being Arm7 and Arm9, which were “good enough.” The real turning point came in 2007: the first iPhone turned “mobile internet” into a necessity, and the smartphone category exploded. Arm became the “most attractive choice” for mobile SoCs due to the PPA advantages of Cortex-A8/A9, with shipments and ecosystem expanding rapidly. After tasting success in the terminal market, Arm then initiated the 64-bit architecture (AArch64) around 2012, advancing into servers and high-performance computing. In other words, Arm’s rise was not a single-point technological breakthrough but a multiplicative effect of “popular terminal demand + ecosystem closure”: first completing scale expansion through smartphones, then leveraging that to penetrate high-end scenarios.
Therefore, it is challenging for RISC-V to succeed in existing markets such as mobile, PC, and servers, as RISC-V will inevitably have disadvantages compared to the existing ecosystem, and its growth will require the impetus of emerging industries.
Tang Dan revealed: “At the beginning of 2024, the RISC-V International Foundation emphasized that the focus of RISC-V development will be AI. Now, there is a consensus across the industry that the blockbuster application of RISC-V will be AI, and some even believe that RISC-V was born for AI.”
In this regard, Tang Dan further explained: “The characteristics of RISC-V are that it is free and highly extensible. For AI applications, in RISC-V, if you think of something, you can modify it, and once modified, you can test it. The issue with AI is that algorithms are still evolving; for example, the instruction sets used for deep learning AI a year ago are different from those for today’s large models. However, expanding instruction sets in x86 and Arm comes with a heavy historical burden, requiring consideration of long-term compatibility, making instruction set expansion relatively cautious.”
Final Thoughts
Twenty years ago, there was a website called OpenCores, where small IPs like UART, I²C, SPI, Ethernet, PCIe, etc., could be downloaded. At that time, the website proposed the OpenRISC instruction set, which was also open but did not develop successfully.
Why did it not develop? There are three reasons. The first is its limited positioning; OpenRISC mainly targeted embedded applications and did not define a complete instruction set. The second is that OpenRISC did not form an organizational structure like a foundation. The third, and most importantly, is that the timing was too early; although some companies adopted this instruction set for products, the overall commercial landing did not take off.
In contrast, RISC-V was born at the intersection of the explosive demand for mobile internet, cloud computing, and AI, with its complete instruction set architecture, modular extension features, open governance model, and rapidly developing software and hardware ecosystem, embodying the perfect combination of “timing, location, and human harmony.”
Today, the commercialization process of RISC-V has fully accelerated, and its momentum towards the high-end market is unstoppable.
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