Bu Zeng – Huawai Micro:
This week, we studied the first half of Chapter 6.
In integrated circuit design, the basic characteristics of devices and the layout design are crucial. It is not a good idea to rely on the absolute values of devices, so using proportional design is evident. However, proportional design still faces the impact of mismatches. Factors affecting the matching of 2D or 3D processes include device size, environmental conditions, parameter gradient distribution within a certain area, temperature differences, etc. The secondary effects of layout are also factors that influence the electrical characteristics and matching properties of devices, so it is essential to minimize the impact of secondary effects.
Chen Qing – Huachuang Micro:
This week, the main content studied was from Chapter 6 to Section 6.4.
1. Psychological Discussion
This chapter mainly introduces the common mechanisms of mismatch formation in integrated circuits from the perspective of process manufacturing and simple improvement methods. The author is quite familiar with process manufacturing and covers a broad range of topics.
2. Summary of Key Knowledge Points
This chapter, up to Section 6.4, first explains the importance of proportional matching, followed by the introduction of offsets and random matching in matching circuits. Finally, it discusses the origins of offset and corresponding handling methods in relation to layout design and various factors in process manufacturing. The main knowledge points are as follows:
(1) Size differences lead to offsets, typically in shrink processes where rounding decisions result in identical sizes being manufactured differently.
(2) The influence of parasitic devices, such as wiring resistance on power or ground lines causing potential differences.
(3) Considerations for matching capacitors and resistors, where capacitors need to account for coupling introduced by wiring, and resistors need to consider value differences caused by intermediate taps.
(4) The impact of gradients, including Linear and Temperature Gradients.
(5) The effects of photolithography, proximity effects, ion implantation, stress, metal lines, etc., on mismatches.
Ziyang Zhou – Suzhou Kaiweite:
This week, we studied Chapter 6 of the ADC.
Chapter 6 mainly explains various deviations and mismatches in wafer production, how to avoid mismatches and deviations in modern processes, and how modern processes reduce these errors. For example, a typical mistake in layout design is if the connection method of the power BUS – power – device – device leads to the connection impedance of the device becoming a source of error. For instance, if the bottom line connects to the source of an Nmos, it will create an error of δVGS, so the layout must adopt the connection method of the power BUS – power – device. Then, the selection of devices must consider whether the device process and the circuit’s performance requirements match, such as high precision, small values, etc. Sometimes, to save costs, it is extremely avoided to have a single device requiring an additional MASK layer, as the cost of producing a MASK in advanced processes is measured in W. Finally, the process of advancing technology step by step includes photolithography correction, dummy modules, STI, etc.
Wang Zhen – China Information Science and Technology::
This week, I systematically studied the section on deterministic and random errors in Chapter 6 of the book “Analog-to-Digital Conversion” focusing on the impact of different devices in layout and process manufacturing.