From the small-scale power cycling and reset during controller debugging to the large-scale unforeseen shutdowns of power networks, every situation constantly tests the reliability of devices. High-end and complex control systems particularly highlight engineers’ attention to detail in their response mechanisms and protective measures against sudden power loss.
NAND Flash/eMMC (NAND Flash with a Flash controller) serves as a cost-effective solution for implementing large-capacity solid-state storage. NAND Flash memory offers advantages such as large capacity and fast rewrite speeds, making it suitable for storing large amounts of data, and it is increasingly applied across various industries, including embedded products, smartphones, and cloud storage databases.
Figure 1: NAND Flash and eMMC Chips
1. Lifespan of Memory Devices
The occurrence of data loss or program disappearance on motherboards using NAND Flash is a nightmare for countless engineers. Watching a program disappear mid-operation can be frustrating, leaving engineers helpless. Experienced engineers may quickly replace the faulty component, working late into the night to patch the code and keep the project afloat. However, simply switching out a few NAND Flash chips is a temporary fix; it is essential to investigate the root cause of the problem, as throwing money at the issue will not resolve it.
Data sheets for these devices typically state that NAND Flash has a block erase lifespan of up to 100,000 cycles, while eMMC can reach up to 10,000 cycles. Similarly, EEPROM, SD cards, CF cards, USB drives, and Flash hard drives all have write lifespan limitations. When the file system writes data to the underlying storage blocks, it usually reads the existing data from the block, erases it, and then rewrites the new data along with the previously read data. If the file system does not manage write balancing effectively, especially with frequent operations requiring data logging within one minute, it can lead to block wear-out in NAND Flash or eMMC.
2. Data Loss Due to Power Failure
When the file system writes data to storage, it typically reads the existing data from the block, erases it, and then rewrites the new data along with the previously read data. If a power failure or voltage instability occurs during the block erasure or data rewriting process, it can result in data loss or corruption. If the lost data includes the FAT table of the file system, it can lead to catastrophic system crashes, preventing the program from starting.
3. System Data Protection Solutions
Often, products do not exhibit program loss before leaving the factory, even after extensive testing and programming. This may be due to the testing equipment ensuring stable power output during operation, allowing the normal Flash protection mechanisms to function reliably.
To prevent Flash damage in actual user environments, strict adherence to product usage instructions is necessary, particularly avoiding sudden power loss during Flash erasure or writing processes. This is a significant taboo in the usage of memory devices; even if the device is functioning correctly, such improper use can significantly shorten its lifespan. Additionally, power systems vary widely in different environments, and if the power supply does not meet the required power levels, the program’s detection threshold for low power may be too low. Forcing the system to start or perform write operations under these conditions can exacerbate power fluctuations, leading to erroneous operations by the CPU on the storage.
To address this issue from a software perspective:
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During debugging or field use, it is recommended to use software resets instead of frequently cutting power for resets. If a power cut is necessary, include print statements such as “System Load Complete” or “Data Saved Successfully” before proceeding;
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Implement Flash wear leveling algorithms in software to efficiently adjust the size of the Flash areas being erased when data changes;
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Consider writing data first to memory or ferroelectric memory, then periodically transferring it to larger storage to reduce direct erase cycles on NAND Flash or eMMC;
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Incorporate or raise the power detection threshold in the program to ensure that all chips in the power system operate normally above this threshold;
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Carefully maintain and update the bad block table during read/write operations to avoid writing to bad blocks. Ensure ECC checks during data reads to confirm data integrity.
From a hardware perspective, attention should be paid to:
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Avoid sudden power loss during Flash erasure or writing processes;
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Design a robust power system for the control core to prevent ripple effects caused by transient changes during CPU startup and operation;
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Incorporate power loss detection circuits that can quickly shut down the file system and stop write operations when external power loss is detected;
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Add UPS power supplies for the file system power domain, or even a backup power supply for the entire system;
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For users utilizing small-capacity storage like EEPROM, consider replacing it with high-reliability ferroelectric non-volatile memory (FRAM) made from ferroelectric materials. FRAM can read and write as quickly as RAM, retains data for up to 10 years after power loss, and has a write lifespan of up to 10 billion cycles, making it more reliable than EEPROM and other non-volatile memory systems, with a simpler structure and lower power consumption.
Figure 2: Ferroelectric Non-Volatile Memory
Below is a brief introduction to a UPS circuit design based on supercapacitors, with key points as follows:
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Due to individual differences in capacitors, the rate at which they store charge varies, leading to potential overcharging and exceeding voltage ratings. When multiple supercapacitors are used in a circuit, voltage balancing is necessary;
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To ensure the capacitors can be fully charged, a constant current source should be used for charging;
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To maintain stable capacitor voltage and reduce power consumption in the charging circuit, over-voltage detection circuits should be added;
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If providing backup power to a system with a voltage higher than the supercapacitor’s maximum voltage, the Vcc_backup terminal should be connected through a BOOST circuit, ensuring the EN pin is turned off during normal operation (charging).
Figure 3: Core Circuit of UPS Based on Supercapacitors
When the system power is normal, the charging circuit charges the UPS. During power loss, the UPS discharges to provide backup power to the system. It is recommended that the UPS can sustain power to the file system for at least 10 seconds after a power loss. During this 10-second backup period, the system can report the abnormal power status, temporarily retain critical data, and shut down the file system to ensure system stability and prevent damage to the file system, which could affect the normal startup of applications.
Figure 4: Recommended UPS Charge/Discharge Timing
Additionally, a power loss detection circuit is necessary. A comparator device can be used, powered by the Output_VCC terminal to ensure it remains operational during external power loss. The negative terminal of the comparator connects to a reference voltage provided by a Zener diode. Under normal power conditions, the comparator’s output voltage is determined by the feedback voltage divider from the boost circuit; during power loss, the comparator outputs a low level, allowing the processor to respond promptly to the status information. Another power loss detection line can be used for other functions.
Figure 5: System Power Loss Detection Circuit
4. Industrial Quality Stability and Reliability
In the fields of ARM core boards, development boards, and industrial computers, products such as the M6708 core board, M/A335x core board, M/A28x core board, EPC series industrial motherboards, IoT series wireless motherboards/gateways, and DCP series classic industrial computers have comprehensive bad block management for NAND Flash and added power loss protection for industrial motherboards. For example, strengthening Flash drivers under Linux systems, implementing dual backups for the operating system, and conducting 100,000 power loss tests on Flash through software and hardware signal testing.
At the same time, Zhiyuan Electronics is equipped with professional EMC laboratories, safety regulation laboratories, and environmental laboratories to simulate harsh application conditions. Collaborating with high-quality suppliers ensures that all discrete components meet EMC industrial level 3 standards, providing good electrostatic resistance, lightning surge resistance, electrical transient group pulse resistance, and extremely low EMI conduction interference; achieving industrial-grade environmental adaptability from -40℃ to +85℃. This provides practical guarantees for the reliability, safety, and stability of the entire target system from Flash to the complete system.
Figure 6: DCP-1000L Product Analysis Diagram
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