FutureAI is expected to continuously iterate the technology path of PCB processes direction
With the continuous iteration of new processes, what potential technological innovations lie ahead?
As AI computing hardware evolves towards high density and high bandwidth, reducing the dielectric constant (dk) and dielectric loss (df) becomes key to breaking transmission bottlenecks. The future of AI in PCB process technology is expected to continue iterating, manifested in structural integration (CoWoP, substrate-based), functional upgrades (orthogonal backplane replacing copper connections), and material breakthroughs (M9, PTFE, quartz cloth, etc.).
1. Iteration Directions of Technology Paths
The rapid development of AI computing hardware is driving PCB process technology towards higher density and higher bandwidth, specifically reflected in the following three core areas:
1. Structural IntegrationThe demand for high-density interconnections in AI hardware has spurred the application of advanced packaging technologies, mainly including:
Chip-on-Wafer-on-Package (CoWoP): Directly stacking chips on the packaging substrate shortens signal transmission paths and enhances integration.
Substrate-based: Achieving finer line spacing through substrate-like (SLP) technology to meet the miniaturization and high pin count requirements of GPU/ASIC chips.
2. Functional Upgrades
Orthogonal backplane replacing copper connections: Traditional copper connections suffer from high signal loss and bandwidth limitations. The orthogonal backplane (Orthogonal Backplane) adopts a vertical crossing structure, significantly reducing signal crosstalk and supporting high-speed transmission above 112Gbps, becoming a key technology for data centers and AI servers.
High-layer boards (>20 layers) design: AI computing hardware (such as GPU boards) needs to optimize wiring space by increasing the number of layers, enhancing signal integrity and power integrity.
3. Material BreakthroughsTo reduce the dielectric constant (dk) and dielectric loss (df), new substrate materials become the core breakthrough:
High-frequency materials: Such as PTFE (polytetrafluoroethylene), M9 (low-loss resin), quartz cloth, etc., with ultra-low dk values (≤3.5) and df values (≤0.003), suitable for high-frequency/millimeter-wave scenarios.
High-performance resin systems: Such as BT resin, PPO, etc., enhancing heat resistance and mechanical strength, suitable for high-power AI chip operating environments.
2. Structural Integration: Reconstructing the boundary between packaging and PCB
1. CoWoP (Chip on Wafer on PCB) Technology
Technical Principle: Eliminating traditional ABF substrates, directly bonding GPU/TPU bare chips to multilayer PCBs with a silicon interlayer, achieving a “packaging substrate + PCB” integration, shortening signal paths by 30% and improving heat dissipation efficiency by 15-20%.
Core Breakthrough:
Process Requirements: Using mSAP (semi-additive process) technology, relying on 2-3μm ultra-thin peelable copper foil (DTH) to achieve micron-level line precision, with copper foil uniformity tolerance required to be ≤±0.5μm.
Material Upgrade: The use of Low CTE glass cloth (thermal expansion coefficient ≤3.2) has surged, requiring 16 sheets for 7-layer HDI PCBs per square meter (compared to only 1 sheet for traditional 5-layer).
Market Space: The global CoWoP PCB market size may reach 80 billion yuan by 2027, with demand for NVIDIA’s GB300 accelerator card accounting for 60%.
2. Substrate-based Trend
Technical Path: PCBs undertake substrate functions, supporting 224G SerDes high-speed interconnections, with the number of layers jumping to 20-46 layers (traditional servers only have 8-16 layers).
Performance Indicators: Impedance control accuracy ±5%, inter-layer alignment ≤75μm, yield must stabilize above 85%.
⚡ 3. Functional Upgrades: High-speed transmission and energy efficiency optimization
1. Orthogonal backplane replacing copper connections
Technical Advantages: Replacing copper cables with vertical orthogonal circuit boards, signal density increases by 3 times, power consumption decreases by 40%, with Huawei’s 384 super orthogonal backplane priced at 200,000 yuan/m².
Application Scenarios: NVIDIA’s GB200 cabinet, 3.2T optical module (mass production in 2027).
2. Power Integrity Innovation
Thick copper foil design: Using 2oz thick copper foil + multiple power planes, supporting 80A large current output, with power supply ripple controlled within ±2%.
Embedded heat dissipation technology: Copper substrate + heat pipe embedded structure, thermal conductivity increased to 5W/(m·K), chip junction temperature ≤85℃ (ambient temperature 40℃).
4. Material Breakthroughs: High-frequency low-loss and domestic substitution
1. High-frequency substrates (M9/PTFE/quartz cloth)
Performance Requirements: Dielectric constant (Dk) ≤3.0, dielectric loss (Df) ≤0.001, signal loss in the 10GHz frequency band ≤0.25dB/in.
Domestic Breakthrough:
M8 copper-clad laminates: Domestic costs are 30% lower than imports, certified by NVIDIA (Df ≤0.001).
Quartz cloth: Demand for Low CTE glass cloth may reach 10 million m² by 2027 (5 billion yuan market).
2. Ultra-thin copper foil (DTH)
Technical Positioning: The processing cost of 2-3μm peelable copper foil reaches 200 yuan/kg (traditional copper foil 60-80 yuan), with a gross margin exceeding 60%.
Domestic Substitution: Fangbang Co., Ltd. acquired Luxembourg copper foil, becoming one of the only two non-Japanese suppliers globally.
5. Core Beneficiaries and Technical Positioning in A-shares
1. Structural Integration (CoWoP/Substrate-based)
|
Target |
Technical Advantages |
Capacity/Orders |
|
Shenghong Technology (300476) |
Core supplier for NVIDIA accelerator cards,mature CoWoP process |
Accelerator card market share75%, 2026 orders scheduled for 20 weeks |
|
Shenzhen Circuit (002916) |
95% yield for high-layer boards above 20 layers, inter-layer alignment accuracy ≤25μm |
Nantong50,000 m² high-end HDI factory to be put into production by the end of 2025 |
|
Pengding Holdings (002938) |
Leading global mSAP process, thin plate SLP technology compatible with CoWoP |
Main supplier for NVIDIA’s GB300 UBB board |
2. Material Breakthroughs (High-frequency substrates/copper foil/glass cloth)
|
Target |
Technical Advantages |
Progress in Domestic Substitution |
|
Honghe Technology (603256) |
Leading Low DK glass cloth technology, CTE ≤3.2 |
Second-generation product mass production, supplying NVIDIA accelerator cards |
|
Fangbang Co., Ltd. (688020) |
Market share of peelable copper foil60%, 3μm DTH copper foil validated |
Acquired Luxembourg copper foil, entering NVIDIA supply chain |
|
Lianrui New Materials (688300) |
Low-α spherical silicon (key filler for CoWoP), purity ≥99.9999% |
Entered TSMC’s CoWoS supply chain |
3. Functional Upgrades (Orthogonal backplane/heat dissipation)
|
Target |
Technical Advantages |
Application Scenarios |
|
Hudian Co., Ltd. (002463) |
Ultra-high-speed backplane technology, supporting112Gbps transmission |
Main PCB supplier for NVIDIA switches |
|
Zhonying Technology (300936) |
Pioneer in domestic PTFE substrate, Df ≤0.0008 |
Huawei5G base station, optical module certification passed |
5. Risks and Trends Outlook
Technical Implementation Risks: CoWoP needs to address the mismatch in thermal expansion coefficients between chips and PCBs; if the yield falls below 80%, commercialization will be delayed.
Substitution Pace: ABF substrates still dominate advanced packaging, with CoWoP penetration expected to be only 30% by 2027.
Domestic Substitution Bottlenecks: The domestic rate of laser drilling machines (precision ≤30μm) is less than 40%, with import equipment delivery times of 8-10 months.