Since we are starting from an example, we need to determine the overall scheme and relevant specifications. Based on this, we must design each module according to the workflow and determine the matching connection methods between them. This example begins processing from the intermediate frequency (IF) signal sampling. Following the mature scheme of the receiver, the workflow involves processing the sampled signal, first capturing the PN code, tracking synchronization, despreading, carrier synchronization, and demodulating the data. Accordingly, the following simplified diagram is obtained.
Briefly explaining the above diagram: (1) The data demodulation uses a typical Costas loop for carrier synchronization. The extraction part in the diagram is intended to reduce the amount of data processing, depending on the chip processing capability; it is not mandatory. (2) The code capture and tracking part actually consists of two parts, each composed of relatively complex loop circuits. This has been simplified here, and a detailed drawing will be provided in the subsequent introduction of the production process.
Having determined the structure, we will now confirm the working specifications. For the purpose of learning through practice, we will start processing from the digitization of the intermediate frequency signal without adopting the zero intermediate frequency scheme. The intermediate frequency is 10.08 MHz, the sampling frequency is 50.4 MHz (5 times sampling), the signal code frequency is 32 kHz, the PN code length is 63 bits, and the spread spectrum code rate is 2016 kHz. It can be seen that each spread spectrum chip contains 5 cycles of the intermediate frequency carrier. The timing relationships of the signal are shown in the diagram below.
Having confirmed the specifications and scheme, the next step is to proceed with simulation and design based on this.