Clock constraint commands in Vivado
create_clock
create_clock -name <name> -period <period> -waveform {<rise_name> <fall_name> } {get_ports <input_port>}
create_clock is used to create the primary clock
create_clock -name <clk0> -period <10.000> -waveform {0 5} {get_ports clk0} (default state)
create_clock -name <clk1> -period <10.000> -waveform {2 8} {get_ports clk1}
create_generated_clock
create_generated_clock is used to constrain derived clocks generated within the FPGA
create_generated_clock -name <generated_clock_name>
-source <master_clock_source_pin_or_port>
-multiply_by <mult_factor>
(how many times the source clock is multiplied)
-divide_by <div_factor>
(how many times the source clock is divided)
-master_clock <master_clk>
(the upper-level clock, which can be the master clock or another derived clock)
<pin_or_port>
set_clock_groups
set_clock_groups -asynchronous -group <clock_name_1> -group <clock_name_2>
set_clock_groups -physically_exclusive -group <clock_name_1> -group <clock_name_2>
The first method: specify that the two master clocks are asynchronous
create_clock -period 10 -name clk1 [get_ports clk1]
create_clock -period 8 -name clk2 [get_ports clk2]
set_clock_groups -asynchronous -group clk1 -group clk2
The second method: when we need to verify whether the same clock port can achieve timing closure under different clock frequencies, for example, there are two asynchronous master clocks clk1 and clk2, we need to verify the timing closure when clk2 frequency is 100MHz, and clk1 frequency is 50MHz, 100MHz, and 200MHz respectively. create_clock -name clk1A -period 20.0 [get_ports clk1]
create_clock -name clk1B -period 10.0 [get_ports clk1] -add
create_clock -name clk1C -period 5.0 [get_ports clk1] -add
create_clock -name clk2 -period 10.0 [get_ports clk2]
set_clock_groups -physically_exclusive -group clk1A -group clk1B -group clk1C
set_clock_groups -asynchronous -group “clk1A clk1B clk1C” -group clk2
The third usage: when we use BUFGMUX, there will be two input clocks, but only one clock will be used. For example, when the MMCM inputs a 100MHz clock, the two outputs are 50MHz and 200MHz, which enter the BUFGMUX. In this case, the timing constraints we need to set are as follows:
set_clock_groups -logically_exclusive
-group [get_clocks -of [get_pins inst_mmcm/inst/mmcm_adv_inst/CLKOUT0]]
-group [get_clocks -of [get_pins inst_mmcm/inst/mmcm_adv_inst/CLKOUT1]]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets xxx]
Declare that the tool is allowed to treat clock signals as ordinary signals
set_property DONT_TOUCH true [get_cells xxx]
Declare not to optimize the specified object