Essential Knowledge on Embedded IoT System Hardware and Software

This article mainly introduces the basic knowledge of embedded systems, covering various aspects of embedded software and hardware, hoping to be helpful to everyone.

Basics of Embedded Systems

1. Definition of Embedded Systems

(1) Definition: A dedicated computer system centered on applications, based on computer technology, with customizable hardware and software, designed to meet strict requirements for functionality, reliability, cost, size, and power consumption of application systems.

(2) Four stages of embedded system development: no operating system stage, simple operating system stage, real-time operating system stage, Internet-oriented stage.

(3) Intellectual Property Core (IP Core): A functional module with intellectual property rights that is specific in function, standardized in interface, and reusable in multiple integrated circuit designs, serving as the basic component for system-on-chip (SoC) implementation.

(4) IP core modules can be designed at three different levels: behavioral, structural, and physical, corresponding to three types of functional behavior descriptions: soft core, firm core, and hard core.

2. Composition of Embedded Systems

Embedded systems consist of: hardware layer, intermediate layer, system software layer, and application software layer.

• Embedded Core Module = Microprocessor + Power Circuit + Clock Circuit + Memory

• Cache: Located between the main memory and the embedded microprocessor core, it stores the most frequently used program code and data in a recent period. Its main goal is to reduce the memory access bottleneck caused by the memory to the microprocessor core, thus speeding up processing.

(1) Hardware Layer: Embedded microprocessor, memory, general device interfaces, and I/O interfaces.

(2) Intermediate Layer (also known as Hardware Abstraction Layer HAL or Board Support Package BSP). It separates the upper-level software from the lower-level hardware, allowing upper-level software developers to develop based on the interfaces provided by the BSP layer without concerning themselves with the specifics of the lower-level hardware.

• BSP has hardware and operating system relevance. Designing a complete BSP requires completing two parts of work:

A. Hardware initialization of the embedded system and BSP functions.

• Chip-level initialization: A purely hardware initialization process that gradually sets the embedded microprocessor from the default state upon power-up to the operational state required by the system.

• Board-level initialization: An initialization process that includes both hardware and software, establishing the operational environment for subsequent system initialization and application programs.

• System-level initialization: A software-centric initialization process for operating system initialization.

B. Designing hardware-related device drivers.

(3) System Software Layer: Composed of RTOS, file systems, GUI, network systems, and general component modules. RTOS serves as the foundation and development platform for embedded application software.

(4) Application Software: Composed of applications developed based on real-time systems.

3. Real-Time Systems

(1) Definition: A system that can complete functional tasks and respond to external or internal events, synchronously or asynchronously, within specified or determined time.

(2) Distinction: General systems typically pursue average response time and user convenience, while real-time systems primarily consider worst-case system behavior.

(3) Characteristics: Time constraints, predictability, reliability, and interactivity with the external environment.

(4) Hard Real-Time (Strong Real-Time): Refers to applications where time requirements must be fully met; otherwise, it could lead to significant safety incidents or substantial losses in life and property, such as in aerospace and military applications.

(5) Soft Real-Time (Weak Real-Time): Refers to applications that, while having time requirements, do not cause severe impacts on system operation or the environment if real-time tasks occasionally violate these requirements, such as monitoring systems and real-time information collection systems.

(6) Task constraints include: time constraints, resource constraints, execution order constraints, and performance constraints.

4. Scheduling in Real-Time Systems

(1) Scheduling: The entire process of determining when and where each real-time task will execute, given a set of real-time tasks and system resources.

(2) Preemptive Scheduling: Usually priority-driven scheduling, such as uCOS. Advantages include good real-time performance and quick response, with relatively simple scheduling algorithms that can guarantee time constraints for high-priority tasks; disadvantages include frequent context switching.

(3) Non-Preemptive Scheduling: Scheduling typically allocated by time slices, where tasks cannot be interrupted during execution; once a task occupies the processor, it must finish execution or voluntarily relinquish control, such as in WinCE. Advantages include fewer context switches; disadvantages include low effective resource utilization of the processor and poor schedulability.

(4) Static Table-Driven Strategy: The system generates a runtime schedule based on the time constraints and relationships of each task before running, indicating the start time and duration of each task.

(5) Priority-Driven Strategy: Determines the execution order of tasks based on their priority levels.

(6) Classification of Real-Time Tasks: Periodic tasks, sporadic tasks, and aperiodic tasks.

(7) General structural model of real-time systems: Data collection tasks implement sensor data acquisition, data processing tasks handle collected data, and processed data is sent to actuators for management tasks to control execution.

5. Architecture of Embedded Microprocessors

(1) Von Neumann Architecture: Programs and data share the same storage space, with program instruction storage addresses and data storage addresses pointing to different physical locations in the same memory, using a single address and data bus with the same width for both. Examples include: 8086, ARM7, MIPS…

(2) Harvard Architecture: Programs and data are stored in two independent memory units, each with separate addressability and access, forming a memory structure that separates program storage from data storage. Examples include: AVR, ARM9, ARM10…

(3) Comparison of CISC and RISC characteristics.

The time P required for a computer to execute a program can be calculated using the formula P = I × CPI × T, where:

• I: The number of instructions executed by the high-level language program after compilation on the machine.

• CPI: The average number of cycles required to execute each instruction.

• T: The time for each machine cycle.

(4) The concept of pipelining: In the CPU, the serial execution process of a single instruction is transformed into overlapping execution of several instruction subprocesses within the CPU.

(5) Pipelining metrics:

• Throughput: The number of results produced by the pipeline processing machine in a unit time. If the times for subprocesses in the pipeline are not the same, the throughput should be the reciprocal of the longest subprocess.

• Setup Time: The time from when the pipeline starts working until it reaches maximum throughput. If m subprocesses take the same time, t, then setup time T = mt.

(6) Byte Order of Information Storage:

• A. Memory unit: Byte (8 bits)

• B. Word length determines the addressing capability of the microprocessor, i.e., the size of the virtual address space.

• C. The virtual address space of a 32-bit microprocessor is 2^32, i.e., 4GB.

• D. Little-endian byte order: Low byte is at low memory address, high byte is at high memory address.

• E. Big-endian byte order: High byte is at low memory address, low byte is at high memory address.

• F. The storage order of network devices depends on the data link layer in the OSI model.

6. Basics of Logic Circuits

(1) Logic circuits are classified as: combinational logic circuits and sequential logic circuits based on whether they have storage functions.

(2) Combinational logic circuits: The output of the circuit at any moment depends only on the input signals at that moment and is independent of the previous state of the circuit. Common logic circuits include decoders and multiplexers.

(3) Sequential logic circuits: The output of the circuit at any moment depends not only on the input at that moment but also on the current state of the circuit. Therefore, the sequential circuit must include memory elements. Flip-flops are the foundation of sequential logic circuits. Common sequential logic circuits include registers and counters.

(4) Truth tables, Boolean algebra, De Morgan’s laws, and the concept of gate circuits.

(5) NOR (not-or) and NAND (not-and) gate circuits are called universal gate circuits, as they can implement any logical function.

(6) Decoder: A combinational logic network with multiple inputs and outputs. Each input of an n-bit binary code can have at most one valid output among m outputs.

When m = 2^n, it is a full decoder; when m < 2^n, it is a partial decoder.

(7) Due to the low high-level output current of integrated circuits and relatively high low-level output current, when directly driving LEDs with integrated gate circuits, low-level driving is often used. LCD seven-segment character displays utilize the different optical characteristics of liquid crystals with and without an external electric field to display characters.

(8) Clock signals are the basis of sequential logic, used to determine when to update the states in logic units. Synchronization is a primary constraint in clock-controlled systems.

(9) When selecting flip-flops, the triggering method is a crucial factor. There are two triggering methods:

Level-triggered: Simple structure, commonly used to form latches.

Edge-triggered: Strong ability to resist data line interference, commonly used to form registers and counters.

7. Bus Circuits and Signal Driving

(1) A bus is a collection of various signal lines, serving as a common pathway for transmitting data, addresses, and control information between components in an embedded system. At any given time, each pathway can transmit one binary signal. Based on the type of information transmitted by the bus, it can be classified into: data bus (DB), address bus (AB), and control bus (CB).

(2) Main parameters of the bus:

• Bus bandwidth: The amount of data that can be transmitted over the bus within a certain time, generally measured in MByte/s.

• Bus width: The number of bits that can be transmitted simultaneously by the bus (bit), commonly referred to as the bus width concept, such as 32-bit or 64-bit. The wider the bus width, the greater the data transmission rate per second.

• Bus frequency: The operating clock frequency measured in MHz; the higher the operating frequency, the faster the bus operates, and thus the wider the bus bandwidth.

• Bus bandwidth = Bus width × Bus frequency / 8, measured in MBps.

• Common buses: ISA bus, PCI bus, IIC bus, SPI bus, PC104 bus, and CAN bus.

(3) Only devices with tri-state outputs can connect to the data bus; the most common tri-state gate is the output buffer.

(4) When the load connected to the bus exceeds its load capacity, a buffer or driver must be added between the bus and the load, the most common being a tri-state buffer, which serves to drive and isolate.

(5) Using bus multiplexing technology can achieve shared data and address buses. However, this brings two issues:

• A. Additional external circuitry is needed to decouple the bus signals, such as address latches.

• B. The bus speed is relatively low compared to non-multiplexed bus systems.

(6) Two types of bus communication protocols: synchronous and asynchronous.

(7) Solving bus arbitration issues is based on the concept of priority.

8. Level Conversion Circuits

(1) Digital integrated circuits can be divided into two main categories: bipolar integrated circuits (TTL) and metal-oxide-semiconductor (MOS).

(2) CMOS circuits are widely used due to their extremely low static power consumption, high operating speed, and strong anti-interference capability.

(3) The solution to the interface difficulties between TTL and CMOS circuits is to connect a pull-up resistor R between the TTL circuit output and the power supply, with the value of the pull-up resistor R determined by the TTL high-level output leakage current IOH; different series of TTL should use different R values.

9. Basics of Programmable Logic Devices

The content in this area should be conceptually understood overall.

10. Basics of Information Representation and Computation in Embedded Systems

(1) Carry counting system and conversion: This is relatively simple, and one should master how to perform conversions, as it may be a test question.

(2) Representation of numbers in computers: source code, one’s complement, and two’s complement.

• The one’s complement of a positive number is the same as its source code, and the one’s complement of a negative number is obtained by inverting the bits of its source code excluding the sign bit.

• The two’s complement of a positive number is the same as its source code, and the two’s complement of a negative number is obtained by adding one to its one’s complement.

• For example, the source code of -98 is: 11100010B

• One’s complement: 10011101B

• Two’s complement: 10011110B

(3) Fixed-point representation: The position of the decimal point is arbitrarily fixed.

• Floating-point representation: The position of the decimal point is variable, consisting of a mantissa and an exponent.

• Any binary N can be expressed as: N = 2^P × S. S is the mantissa, and P is the exponent.

(4) Character representation, understanding the conversion between GB2318-80 Chinese standard code and internal code.

(5) Quantization parameters in speech encoding (may involve simple calculation questions).

• Sampling frequency: The number of samples taken in one second, reflecting the interval between sampling points.

• The upper limit of human hearing is 20kHz, so a sampling frequency above 40kHz is sufficient for human satisfaction.

• The sampling frequency used in CDs is 44.1kHz.

• Measurement accuracy: The quantization level of samples; the current standard sampling levels are 8-bit and 16-bit.

• Number of channels: Mono and stereo. Stereo requires twice the storage space.

11. Error Control Coding

(1) Based on the function of the code group, it can be divided into error detection codes and error correction codes. Error detection codes can automatically detect errors, such as parity check codes; error correction codes can not only detect errors but also automatically correct them, such as cyclic redundancy check codes.

(2) Parity check codes, Hamming codes, cyclic redundancy check codes (CRC).

12. Measurement Items of Embedded Systems

(1) Performance indicators: divided into component performance indicators and comprehensive performance indicators, mainly including throughput, real-time performance, and various utilization rates.

(2) Reliability and safety: Reliability is the most important and prominent basic requirement of embedded systems, ensuring that an embedded system can operate normally, typically measured by mean time between failures (MTBF).

(3) Maintainability: Generally represented by mean time to repair (MTTR).

(4) Availability

(5) Power consumption

(6) Environmental adaptability

(7) Generality

(8) Safety

(9) Confidentiality

(10) Scalability

The cost-performance ratio includes not only the direct purchase price of the embedded system but also installation costs, several years of operating maintenance costs, and software rental fees.

13. Evaluation Methods of Embedded Systems: Measurement Method and Model Method

(1) The measurement method is the most direct and fundamental method, requiring the resolution of two issues:

• A. Determine the system parameters to be measured based on the research purpose.

• B. Select measurement tools and methods.

(2) There are two measurement methods: sampling method and event tracing method.

(3) The model method is divided into analytical model method and simulation model method. The analytical model method uses mathematical equations to depict the system model, while the simulation model method dynamically expresses the state of the embedded system through the operation of simulation programs for statistical analysis and performance indicators.

(4) The most commonly used analytical model method is the queuing model, which consists of three parts: input flow, queuing rules, and service facilities.

(5) Evaluating a system using models requires resolving three issues: designing the model, solving the model, and calibrating and validating the model.

Interface Technology

1. Flash Memory

(1) Flash memory is a type of non-volatile memory, which can be divided into NOR Flash and NAND Flash based on structural differences.

(2) Characteristics of Flash memory:

• A. Block structure: Physically divided into several blocks, with blocks being independent of each other.

• B. Erase-before-write: The write operation of Flash can only change data bits from 1 to 0, not from 0 to 1, so before writing to the memory, an erase operation must be performed to initialize the pre-written data bits to 1. The minimum unit for the erase operation is a block, not a single byte.

• C. Operation instructions: To perform a write operation, a series of special instructions (NOR Flash) or a sequence of timings (NAND Flash) must be input to write data.

• D. Bit inversion: Due to the inherent characteristics of Flash, occasional data errors may occur during read and write processes. Bit inversion cannot be avoided and can only be processed afterward through other means.

• E. Bad blocks: Once a block is damaged, it cannot be repaired. The results of operations on damaged blocks are unpredictable.

(3) Characteristics of NOR Flash:

Application programs can run directly in flash memory without needing to read the code into system RAM. NOR Flash has high transfer efficiency, particularly effective in small capacities between 1MB to 4MB, but its low write and erase speeds significantly affect its performance.

(4) Characteristics of NAND Flash:

NAND Flash achieves very high density units, allowing for high storage density, and has fast write and erase speeds, which is why all USB drives use NAND Flash as the storage medium. The challenge of using NAND Flash lies in the need for a special system interface.

(5) Differences between NOR Flash and NAND Flash:

• A. NOR Flash has slightly faster read speeds than NAND Flash.

• B. NAND Flash has much faster erase and write speeds than NOR Flash.

• C. NAND Flash has poor random read capabilities, suitable for large amounts of continuous data reading.

• D. NOR Flash has an SRAM interface with sufficient address inputs for easy access to each byte internally. NAND Flash shares an 8-bit bus for address, data, and commands (some products use a 16-bit bus), requiring complex I/O interfaces to access data serially.

• E. NOR Flash generally has a smaller capacity, typically between 1MB to 8MB; NAND Flash is only used in products over 8MB. Therefore, NOR Flash is applied in code storage media, while NAND Flash is suitable for data storage.

• F. The maximum erase-write cycle for NAND Flash is one million times, while for NOR Flash it is one hundred thousand times.

• G. NOR Flash can be connected like other memory, used directly, and can run code directly on it; NAND Flash requires special I/O interfaces, and a driver must be written before performing other operations. Designers must never write to bad blocks, which means virtual mapping must be implemented throughout NAND Flash usage.

• H. NOR Flash is used in fields requiring high data reliability, such as code storage, communication products, and network processing; NAND Flash is used in fields requiring high storage capacity, such as MP3 players, storage cards, and USB drives.

2. RAM Memory

(1) Characteristics of SRAM:

SRAM stands for Static Random Access Memory, which retains a value as long as it is powered, without a refresh cycle, and is composed of flip-flops as basic units, having low integration, with each SRAM storage unit consisting of six transistors, making it relatively expensive. It has a high speed and is commonly used in cache memory. Typically, SRAM has four pins:

• CE: Chip select signal, active low.

• R/W: Read/write control signal.

• ADDRESS: A set of address lines.

• DATA: A set of bidirectional signal lines for data transmission.

(2) Characteristics of DRAM:

DRAM stands for Dynamic Random Access Memory. It is a semiconductor memory that stores data in the form of electric charges. Each storage unit consists of a transistor and a capacitor, with data stored in the capacitor. Capacitors lose charge due to leakage, making DRAM devices unstable. They must be refreshed regularly to retain data. DRAM interfaces are relatively complex, typically having the following pins:

• CE: Chip select signal, active low.

• R/W: Read/write control signal.

• RAS: Row address strobe signal, usually connected to the high-order part of the address.

• CAS: Column address strobe signal, usually connected to the low-order part of the address.

• ADDRESS: A set of address lines.

• DATA: A set of bidirectional signal lines for data transmission.

(3) Characteristics of SDRAM:

SDRAM stands for Synchronous Dynamic Random Access Memory. Synchronous means that memory operation requires a synchronized clock, with internal command sending and data transmission based on this clock; dynamic indicates that the memory array must be refreshed continuously to prevent data loss. It typically operates at a main frequency of 133MHz.

(4) Characteristics of DDRAM:

DDRAM stands for Double Data Rate Synchronous Dynamic Random Access Memory, also known as DDR. DDRAM is based on SDRAM technology; SDRAM transmits data once per clock cycle, while DDR memory transmits data twice per clock cycle, once on the rising edge and once on the falling edge. At a main frequency of 133MHz, DDR memory bandwidth can reach 133×64b/8×2 = 2.1GB/s.

3. Hard Disks, Optical Discs, CF Cards, SD Cards

4. GPIO Principles and Structures

GPIO is the most basic form of I/O, consisting of a group of input or output pins. Some GPIO pins can be programmed to change their working direction, typically having two control registers: data register and data direction register. The data direction register sets the direction of the port. If the pin is set to output, the data register controls the state of that pin. If the pin is set to input, the state of this input pin is controlled by the logic circuit layer on the pin.

5. A/D Interface

(1) An A/D converter is a circuit that converts analog electrical quantities into digital quantities. There are many methods to achieve A/D conversion, with the commonly used methods being counting method, dual integration method, and successive approximation method.

(2) Counting A/D conversion method:

The main components of the circuit include: comparator, counter, D/A converter, and standard voltage source.

In simple terms, a counter starts counting from 0, adding 1 each time. Each time it adds 1, that value is used as input to the D/A converter, producing a comparison voltage VO to compare with the input analog voltage VIN. If VO is less than VIN, the counter continues to count up by 1 until VO exceeds VIN, at which point the accumulated value of the counter is the output value of the A/D converter.

This conversion method is simple but relatively slow, especially when the analog voltage is high, as the conversion speed becomes slower. For example, for an 8-bit A/D converter, if the input analog quantity is at its maximum, the counter must count from 0 to 255, performing 255 D/A conversions and voltage comparisons to complete the conversion.

(3) Dual integration A/D conversion method:

The main components of the circuit include: integrator, comparator, counter, and standard voltage source.

Its working principle is that the circuit first integrates the input voltage to be measured over a fixed time, then performs a reverse integration with a standard voltage at a fixed slope, returning to the starting value after a certain time. Since a fixed slope is used, the time taken for reverse integration to return to the starting value is proportional to the input analog voltage value; the higher the input voltage, the longer the time taken. By measuring the time taken for reverse integration with a standard high-frequency clock pulse, the corresponding digital quantity for the input analog voltage can be obtained, completing the A/D conversion.

This method has strong immunity to industrial frequency interference, high conversion accuracy, but slow conversion speed, typically with a conversion frequency of less than 10Hz, mainly used in digital testing instruments and temperature measurement.

(4) Successive approximation A/D conversion method:

The main components of the circuit include: comparator, D/A converter, successive approximation register, and reference voltage source.

Its working principle is essentially a binary search method, similar to the principle of using a balance scale. During A/D conversion, the D/A converter increases the conversion bit from high to low, producing different output voltages to compare the input voltage with the output voltage. First, the highest bit is set to 1, which is equivalent to comparing half of the reference voltage with the input voltage. If the input voltage is less than half of the reference voltage, the highest bit is set to 0; otherwise, it is set to 1. Next, the next highest bit is set to 1, which means performing another binary search within the range of 1/2, and so on, approaching the target successively.

This method is fast, with high conversion accuracy, requiring only M clock pulses to complete for an N-bit A/D converter, and is generally used to measure changes in transition processes of several tens to hundreds of microseconds, making it the most widely used conversion method today.

(5) Important indicators for A/D conversion (may involve some simple calculations):

• A. Resolution: Reflects the A/D converter’s ability to respond to small input changes, usually represented by the voltage level corresponding to the least significant bit (LSB) of digital output. An n-bit A/D converter can reflect 1/2^n of the full-scale analog input level.

• B. Range: The range of analog input voltages that can be converted, divided into unipolar and bipolar types.

• C. Conversion time: The time required to complete one A/D conversion, whose reciprocal is the conversion rate.

• D. Accuracy: Accuracy and resolution are two different concepts; even with high resolution, accuracy may not be high due to temperature drift, linearity, etc. Accuracy can be expressed in absolute and relative terms. Absolute accuracy is usually represented by the fractional value of the least significant bit (LSB), while relative accuracy is expressed as a percentage of the full-scale analog voltage.

• For example, with a full scale of 10V and a 10-bit A/D chip, if its absolute accuracy is ±1/2 LSB, the quantization unit for the least significant bit LSB is: 10/1024 = 9.77mV, with an absolute accuracy of 9.77mV/2 = 4.88mV and relative accuracy of 0.048%.

6. Basics of D/A Interface

(1) D/A converters convert digital quantities into analog quantities.

(2) In integrated circuits, T-type networks are commonly used to realize the conversion of digital quantities into analog currents, which are then converted into analog voltages by operational amplifiers. D/A conversion actually involves these two steps.

(3) Types of D/A converters:

• A. Voltage output type: Commonly used as high-speed D/A converters.

• B. Current output type: Generally used with external operational amplifiers.

• C. Multiplicative type: Can be used as modulators and to digitally attenuate input signals.

(4) Main indicators of D/A converters: resolution, setup time, linearity, conversion accuracy, temperature coefficient.

7. Keyboard Interface

(1) Two forms of keyboards: linear keyboard and matrix keyboard.

(2) There are usually two methods for recognizing closed keys on the keyboard: row scanning method and row inversion method.

(3) The row scanning method is commonly used for recognizing keys on matrix keyboards, which is performed in two steps:

• A. Identify which column key is pressed: Set all row lines to low, checking if any column lines are low. If a column line is low, it indicates that a key in that column is pressed; otherwise, no key is pressed.

• B. If a column has a pressed key, identify which row key is pressed: Set each row to low sequentially while keeping the others high, checking for changes in the column. If a column line changes to low, the key at the intersection of that row and column is confirmed to be pressed.

8. Display Interface

(1) The basic principle of LCD is to control the passage of light by supplying power to different liquid crystal units, achieving the display purpose.

(2) There are two ways to provide light sources for LCD: projection and reflection. The LCD display in laptops is projection-based, with a light source behind the screen, so external light is not required. Generally, the LCDs used in microcontrollers are reflection-based, requiring an external power source and relying on reflected light to function. Electroluminescent (EL) is a method of providing light sources for LCD screens.

(3) Based on the driving method, common LCDs can be divided into three categories: Twisted Nematic (TN), Super Twisted Nematic (STN), and Thin Film Transistor (TFT).

(4) There are two types of LCDs available on the market: LCD display modules with driver circuits, which can be driven using a bus method; and LCD displays without driver circuits, which use controller scanning methods.

(5) Typically, when the LCD controller operates, it requests the bus via DMA, directly reading data from the specified address (display buffer) in SDRAM, which is then converted into the scanning data format for the LCD and directly drives the LCD display.

(6) The VGA interface is essentially an analog interface, generally using a unified 15-pin connector, including 2 NC signals, 3 monitor data bus lines, 5 GND signals, 3 RGB color components, 1 horizontal sync signal, and 1 vertical sync signal. The level standard for color components is defined by the EIA RS343 standard.

9. Touchscreen Interface

(1) Based on the working principle, touchscreens can be divided into: surface acoustic wave screens, capacitive screens, resistive screens, and infrared screens.

(2) Touchscreen control uses specialized chips, such as ADS7843.

10. Audio Interface

(1) Basic principle: Data input from the microphone is decoded by the audio codec to complete A/D conversion, and the decoded audio data is sent to the DSP or CPU for processing via the audio controller, then sent to the audio encoder for D/A conversion and output by the speaker.

(2) There are various formats for digital audio, with the three most common being:

• A. Digital audio (PCM): The data format used by CDs or DVDs. Its sampling frequency is 44.1kHz. When the precision is 16 bits, the PCM audio data rate is 1.41Mb/s; when the precision is 32 bits, it is 2.42 Mb/s. A 700MB CD can store about 60 minutes of 16-bit PCM data format music.

• B. MPEG Layer 3 Audio (MP3): The audio format used by MP3 players. Stereo MP3 data rates range from 112kb/s to 128kb/s.

• C. ATSC Digital Audio Compression Standard (AC3): The digital audio encoding standard for digital TV, HDTV, and movies, with stereo AC3 encoded data rates of 192kb/s.

(3) IIS is a commonly used serial audio digital interface for encoding or decoding audio data. The IIS bus only handles sound data, while other control signals must be transmitted separately. IIS uses three serial buses: data line SD, word select line WS, and clock signal line SCK.

(4) When the data field width of the receiver and sender is different, the sender does not consider the width of the receiver’s data field. If the sender sends a data field smaller than the system field width, it fills in 0s at the low end; if the sender’s data width exceeds the receiver’s width, the excess bits are truncated. The word select WS is used to select the left and right channels, where WS=0 indicates the left channel is selected, and WS=1 indicates the right channel is selected. Additionally, WS allows the receiving device to store the previous byte and prepare to receive the next byte.

11. Serial Interface

(1) Serial communication refers to the transmission of data bit by bit, as opposed to parallel communication. Serial communication has advantages such as fewer transmission lines and lower costs, especially suitable for long-distance transmission; however, it is slower.

(2) There are three basic communication modes for serial data transmission: simplex, half-duplex, and full-duplex.

(3) Serial communication can be divided into two types based on information format: synchronous and asynchronous.

• A. Asynchronous transmission: Each character is treated as independent information and transmitted according to a fixed predetermined timing, but the timing between characters is arbitrary. In asynchronous communication, characters are transmitted frame by frame, each frame being synchronized by a start bit. The interval between codes in a frame is fixed, while the time interval between two adjacent frames is not fixed.

• B. Synchronous transmission: In synchronous mode, not only is the timing between characters synchronized, but the timing between characters remains synchronized as well. Synchronous transmission involves grouping many characters into a character block, adding 1 to 2 synchronization characters before each block of information, and adding appropriate error detection data after the block before transmission.

(4) Asynchronous communication must adhere to three regulations:

• A. Character format: Start bit + data + parity bit + stop bit (parity bit can be omitted), with the low bit transmitted first.

• B. Baud rate: The number of bits transmitted per second.

• C. Parity bit: Odd or even parity.

• a. Odd parity: The number of 1s in the character plus the parity bit must be odd.

• b. Even parity: The number of 1s in the character plus the parity bit must be even.

(5) The electrical characteristics of RS-232C: Negative logic.

• A. On TxD and RxD: Logic 1 is -3V to -15V, and logic 0 is 3V to 15V.

• B. On control lines such as TES, CTS, DTR, DCD, etc.:

• The signal is valid (ON state) at 3V to 15V.

• The signal is invalid (OFF state) at -3V to -15V.

(6) Level conversion between TTL standards and RS-232C standards is achieved using integrated chip RS232.

(7) RS-422 serial communication interface:

• A. RS-422 is a single-machine sending/multi-machine receiving unidirectional, balanced transmission specification, with a transmission rate of up to 10Mb/s.

• B. RS-422 uses differential transmission, also known as balanced transmission, utilizing a pair of twisted wires.

• C. RS-422 requires a termination resistor, with a resistance value approximately equal to the characteristic impedance of the transmission cable.

(8) RS-485 serial bus interface:

• A. RS-485 is a standard established based on RS-422, adding multi-point and bidirectional communication capabilities, with communication distances ranging from several meters to thousands of meters.

• B. RS-485 transceivers utilize balanced transmission and differential reception, providing suppression of common-mode interference.

• C. RS-485 requires two termination resistors. For short distances (less than 300m), termination resistors may not be necessary.

12. Parallel Interface

(1) The data transmission rate of parallel interfaces is 8 times faster than that of serial interfaces, with the standard parallel interface data transmission rate being 1Mb/s, commonly used for connecting printers, scanners, etc., hence also referred to as printer ports.

(2) Parallel interfaces can be divided into SPP (Standard Parallel Port), EPP (Enhanced Parallel Port), and ECP (Extended Parallel Port).

(3) Parallel buses are divided into standard and non-standard categories. Common standard parallel buses include IEEE 488 bus and ANSI SCSI bus. The MXI bus is a high-performance non-standard universal multi-user parallel bus.

13. PCI Interface

(1) The PCI bus is a high-performance 32-bit and 64-bit bus that multiplexes addresses and data, serving as an interconnection mechanism between microprocessors and peripheral control components and additional peripheral boards.

(2) In terms of data width, PCI defines a 32-bit data bus, which can be expanded to 64 bits. In terms of bus speed, there are two types: 33MHz and 66MHz.

(3) Compared to the ISA bus, the PCI bus time-multiplexes the address bus and data bus, supporting plug-and-play, interrupt sharing, and other functions.

14. USB Interface

(1) The main features of USB bus:

• A. Simple to use, plug-and-play.

• B. Each USB system has a host, and up to 127 devices can be connected in this USB network.

• C. Wide application range, supporting multiple devices operating simultaneously.

• D. Low-cost cables and connectors, using a unified 4-pin plug.

• E. Strong error correction capability.

• F. Lower protocol overhead leads to high overall bus performance, suitable for the development of low-cost peripherals.

• G. Supports multiple data streams and message streams transmission between host and devices, as well as synchronous and asynchronous transmission types.

• H. Bus powered, able to provide 5V/100mA power to devices.

(2) The USB system is described in three parts: USB host, USB device, and USB interconnection.

(3) The data transmission rates supported by the USB bus include three types: high-speed signaling rate of 480Mb/s; full-speed signaling rate of 12Mb/s; low-speed signaling rate of 1.5Mb/s.

(4) USB bus cables have four wires: a pair of twisted signal lines and a pair of power lines.

(5) USB is a polling bus, where the main controller initiates all data transmissions. The peripherals connected to the USB share the USB bandwidth through a token-based protocol scheduled by the host.

(6) Most bus transactions involve the transmission of three packets:

• A. Token packet: Indicates what transaction is to be performed on the bus, the USB device to be addressed, and the direction of data transfer.

• B. Data packet: Transmits data or indicates that there is no data to transmit.

• C. Handshake packet: Indicates whether the transmission was successful.

(7) The USB data transmission model between the host and device endpoints is called a pipe. There are two types of pipes: stream and message. Message data has a structure defined by USB, while data streams do not.

(8) The transaction scheduling table allows traffic control for certain stream pipes, using NAK (negative acknowledgment) handshake signals at the hardware level to adjust the data transmission rate, preventing buffer overflows or underflows.

(9) The most notable feature of USB devices is plug-and-play.

(10) Working principle: When a USB device is plugged into a USB endpoint, the host communicates with the device’s endpoint 0 via the default address 0. In this process, the host sends a series of standard requests to obtain descriptors, acquiring all the information of interest about the device, thus understanding the device’s status and how to communicate with it. The host then issues a Set Address request to assign a unique address to the device. After that, the host communicates with the device using the assigned address rather than the default address 0.

15. SPI Interface

(1) SPI is a synchronous protocol interface where all transmissions reference a common clock generated by the host, with the receiving external devices using the clock to synchronize the reception of the serial bit stream.

(2) When multiple devices are connected to the same SPI interface, the host selects the device through the chip select pin of the slave device.

(3) SPI primarily uses four signals: Master Out Slave In (MOSI), Master In Slave Out (MISO), Serial Clock (SCLK), and Slave Select (CS).

(4) Both the host and peripherals contain a serial shift register, and the host initiates a data transfer by writing a byte to its SPI serial register. The register transmits the byte to the peripheral via the MOSI signal line, and the peripheral returns the content of its shift register to the host via the MISO signal line, thus exchanging the content of both shift registers.

(5) The write and read operations of peripherals are completed synchronously, making SPI a very efficient protocol.

(6) If only a write operation is performed, the host can ignore the received byte; conversely, if the host wants to read a byte from the peripheral, it must send a dummy byte to trigger the slave’s transmission.

16. IIC Interface

(1) The IIC bus is a high-performance multi-master bus with bus arbitration and synchronization features for high and low-speed devices.

(2) The IIC bus requires two lines: Serial Data Line (SDA) and Serial Clock Line (SCL).

(3) Each device on the bus has a unique address for identification, and each device can act as either a transmitter or receiver (depending on the device’s function).

(4) The IIC bus has four operating modes: master send, master receive, slave send, and slave receive.

(5) There are three types of signals during data transmission in IIC:

• A. Start signal: SDA transitions from high to low when SCL is low.

• B. Stop signal: SDA transitions from low to high when SCL is low.

• C. Acknowledge signal: The receiver sends a specific low signal to the sender after receiving 8 bits of data.

(6) After the master device sends a start signal, it immediately sends a slave address to notify the slave device that it will communicate with it. One byte of address consists of 7 bits of address information and 1 bit indicating the direction of transmission; if the 7th bit is 0, it indicates a write operation; if it is 1, it indicates a read operation.

(7) Each byte transmitted on the SDA line is 8 bits long, and there is no limit to the number of bytes transmitted at a time. The first byte after the start signal is the address field, and each byte transmitted afterward has an acknowledgment bit (ACK) after it. The most significant bit (MSB) of the serial data is sent first.

(8) If the data receiver can no longer accept more data, it can interrupt the transmission by holding the SCL line low, forcing the data sender to wait until SCL is released again. This allows synchronization between high and low-speed devices.

(9) The working process of the IIC bus: SDA and SCL are both bidirectional. When idle, both SDA and SCL are high. Only when SDA goes low, followed by SCL going low, does the data transmission on the IIC bus begin. Each bit transmitted on the SDA line is sampled on the rising edge of SCL, and that bit must remain valid until SCL goes low again, after which the next bit is transmitted before SCL goes high again, indicating the end of data transmission.

17. Ethernet Interface

(1) The most commonly used Ethernet protocol is the IEEE802.3 standard.

(2) Transmission encoding: Manchester encoding and differential Manchester encoding.

• A. Manchester encoding: Each bit has a level transition in the middle; a transition from high to low represents “0,” while a transition from low to high represents “1.”

• B. Differential Manchester encoding: Each bit has a level transition in the middle, utilizing whether there is a transition at the start of each code element to represent “0” or “1”; a transition indicates “0,” while no transition indicates “1.”

(3) In comparison, Manchester encoding is simpler, while differential Manchester encoding provides better noise suppression performance.

(4) Characteristics of Ethernet data transmission:

• A. The transmission of all data bits starts from the low end, using Manchester encoding for the bit stream.

• B. Ethernet is based on a collision detection bus multiplexing method, executed automatically by hardware.

• C. The length of the transmitted data includes destination address DA + source address SA + type field TYPE + data segment DATA + padding bits, with a minimum of 60B and a maximum of 1514B.

• D. Typically, an Ethernet card can receive data from three address types: broadcast address, multicast address, and its own address.

• E. The physical address of any two network cards is unique, assigned by a dedicated organization.

(5) Embedded Ethernet interfaces can be implemented in two ways:

• A. Embedded processor + network card chip (e.g., RTL8019AS, CS8900, etc.)

• B. Processor with Ethernet interface.

(6) TCP/IP is a layered protocol, consisting of: physical layer, data link layer, network layer, transport layer, and application layer. Each layer implements a specific function, corresponding to one or more transmission protocols, with each layer functioning as an independent data packet relative to its lower layer. The protocols at each layer are as follows:

• A. Application layer: BSD sockets.

• B. Transport layer: TCP, UDP.

• C. Network layer: IP, ARP, ICMP, IGMP.

• D. Data link layer: IEEE802.3 Ethernet MAC.

• E. Physical layer: Binary bit stream.

(7) ARP (Address Resolution Protocol):

• A. The network layer uses a 32-bit address to identify different hosts (i.e., IP addresses), while the link layer uses a 48-bit physical address (MAC) to identify different Ethernet or token ring interfaces.

• B. ARP function: To achieve the conversion from IP address to corresponding physical address.

(8) ICMP (Internet Control Message Protocol):

• A. Used by the IP layer to exchange error messages and other important control information with other hosts or routers.

• B. ICMP messages are transmitted within IP packets.

• C. The network diagnostic tools ping and traceroute are actually ICMP protocols.

(9) IP (Internet Protocol):

• A. IP operates at the network layer and is the core protocol of the TCP/IP protocol suite.

• B. All TCP, UDP, ICMP, and IGMP data are transmitted in IP packet format.

• C. TTL (Time To Live) field: Specifies the lifespan of the IP packet (the number of routers the packet can pass through).

• D. IP provides unreliable, connectionless data packet delivery service, being efficient and flexible.

(10) TCP (Transmission Control Protocol):

TCP protocol is a connection-oriented reliable transport layer protocol, providing high reliability end-to-end data communication between two hosts.

(11) UDP (User Datagram Protocol):

UDP protocol is a connectionless unreliable transport layer protocol, which does not guarantee that data packets will reach their destination; reliability is provided by the application layer. UDP protocol has less overhead and is more suitable for use in low-end embedded fields compared to TCP.

(12) Ports: TCP and UDP use 16-bit port numbers to identify upper-layer users, i.e., application layer protocols, such as TCP port numbers for FTP services being 21, Telnet services being 23, and TFTP services being 69 for UDP.

18. CAN Bus Interface

(1) The CAN (Controller Area Network) bus is a multi-master serial communication bus, one of the most widely used field buses internationally, initially used in electronic control networks in automotive environments. An ideal single network composed of a CAN bus can connect any number of nodes, although in practical applications, the number of nodes is limited by the electrical characteristics of the network hardware.

(2) The bus signal is transmitted using differential voltage. Two signal lines are referred to as CAN_H and CAN_L, with a static voltage of around 2.5V; this state represents logic 1, also called “dominant.” When CAN_H is higher than CAN_L, it represents logic 0, called “recessive,” typically with voltage values of CAN_H = 3.5V and CAN_L = 1.5V.

(3) When both “dominant” and “recessive” bits are sent simultaneously, the final bus value will be “dominant,” which establishes the basis for CAN bus arbitration.

(4) A bit time in the CAN bus can be divided into four parts: synchronization segment, propagation time segment, phase buffer segment 1, and phase buffer segment 2.

(5) CAN bus data frames have two formats: standard format and extended format, including: frame start, arbitration field, control field, data field, CRC field, ACK field, and frame end.

(6) The CAN bus hardware interface includes: CAN bus controller and CAN transceiver. The CAN controller mainly performs tasks such as timing logic conversion, for example, Philips’s SJA1000. The CAN transceiver is the physical layer chip of the CAN bus, converting TTL levels to CAN bus electrical characteristics, such as TJA1050.

19. xDSL Interface

(1) xDSL (Digital Subscriber Line) technology involves connecting dedicated DSL modem devices at both ends of existing user telephone lines, using the high-frequency bandwidth characteristics of digital signals to transmit directly, eliminating the intermediate A/D conversion and breaking through the idle limit of analog signal transmission speed of 56KB/s.

(2) DSL technology is mainly divided into symmetric and asymmetric categories.

(3) Symmetric xDSL is more suitable for point-to-point connections in enterprises, such as file transfers and video conferences, where the data transmission volume is roughly the same in both directions.

(4) ADSL is a recently developed broadband access technology that uses twisted copper wires to provide asymmetric broadband information services in both directions.

(5) ADSL transmits one high-speed downstream data, one lower-speed upstream data, and one analog telephone signal simultaneously over a pair of telephone lines. Different frequency bands are used for each signal, with low frequencies transmitting voice, medium narrowband transmitting upstream channel data and control information, and the remaining high-frequency band transmitting downstream channel data, images, or high-speed data.

20. WLAN Interface

(1) WLAN (Wireless Local Area Network) is established using wireless communication technology within a certain local range, combining computer networks with wireless communication technology to provide the functions of wired local area networks using wireless multi-access channels as transmission media.

(2) WLAN standards: Mainly target physical layer and medium access control layer (MAC layer), involving all the technical specifications and standards for wireless frequency ranges and control interface communication protocols used.

• A. IEEE 802.11: Defines physical layer and MAC layer specifications, operating in the 2.4 to 2.4835GHz frequency range, with a maximum rate of 2Mb/s, being the initial wireless local area network standard set by IEEE.

• B. IEEE 802.11b: Operating in the 2.4 to 2.4835GHz frequency range, with a maximum rate of 11Mb/s, and a transmission distance of 50 to 150 inches. It operates in both point-to-point and basic modes, allowing automatic switching between different rates of 11Mb/s, 5.5Mb/s, 2Mb/s, and 1Mb/s based on actual conditions.

• C. IEEE 802.11a: Operating in the 5.15 to 8.825GHz frequency range, with maximum rates of 54Mb/s/72Mb/s and a transmission distance of 10 to 100m.

• D. IEEE 802.11g: A hybrid standard that has the transmission rate of IEEE 802.11a and better security than IEEE 802.11b, using two modulation methods to achieve compatibility with both IEEE 802.11a and IEEE 802.11b.

(3) WLAN has two types of network: peer-to-peer network and infrastructure network.

21. Bluetooth Interface

(1) The purpose of Bluetooth technology is to achieve seamless resource sharing between specific mobile phones, portable computers, and various portable communication devices within a short distance.

(2) The essence of Bluetooth technology is to establish a universal wireless air interface and its control software open standard. Its working frequency band is the globally common 2.4GHz ISM (Industrial, Scientific, Medical) band, with a data transmission rate of 1Mb/s, using time-division duplexing to achieve full-duplex transmission, with an ideal connection range of 10cm to 10m.

(3) The Bluetooth baseband protocol combines circuit-switched and packet-switched methods.

(4) Characteristics of Bluetooth technology:

• A. Short transmission distance, typically within 10m.

• B. Uses frequency-hopping spread spectrum technology.

• C. Utilizes time-division multiple access technology to effectively avoid issues like “collisions” and “hidden terminals.”

• D. Network technology.

• E. Language support.

• F. Error correction technology, employing the FEC (Forward Error Correction) scheme.

(5) The Bluetooth interface consists of three main units: wireless unit, baseband unit, and link management and control unit.

22. 1394 Interface

(1) 1394 is a standard bus that can bridge communication between different industrial devices, allowing up to 63 devices to be connected on a single bus.

(2) Characteristics of IEEE 1394:

• A. Supports multiple bus speeds to meet different application requirements.

• B. Plug-and-play support, enabling hot-swapping.

• C. Supports both synchronous and asynchronous transmission modes.

• D. Supports point-to-point communication mode; IEEE 1394 is a multi-master bus.

• E. Follows the ANSI IEEE 1212 Control and Status Register (CSR) standard, defining a 64-bit address space that can address 1024 buses with 63 nodes, each node capable of containing 256TB of memory space.

• F. Supports long-distance transmission.

• G. Supports fair arbitration principles, ensuring sufficient transmission bandwidth for each transmission type.

• H. Six-wire cables include power lines, capable of transmitting 8 to 40V of DC voltage.

(3) The IEEE 1394 protocol stack consists of three layers: physical layer, link layer, and transaction layer, along with an additional management layer. The physical layer and link layer are hardware-based, while the transaction layer is primarily software-implemented.

• A. The physical layer provides the electrical and mechanical interfaces for IEEE 1394, responsible for reassembling byte streams and sending them to the destination nodes.

• B. The link layer provides data services for the transaction layer, including addressing, data framing, and data verification.

• C. The transaction layer provides services for applications.

• D. The management layer defines all protocols, services, and processes used by a management node.

23. Power Interface

(1) DC-DC converters have three types:

• A. Linear regulators: Produce a voltage lower than the input voltage.

• B. Switching regulators: Can increase, decrease, or invert the input voltage.

• C. Charge pumps: Can increase, decrease, or invert the input voltage, but have limited current driving capability.

(2) No transformer conversion process achieves 100% efficiency; regulators themselves also consume current (static current), which comes from input current. The larger the static current, the greater the power consumption of the regulator.

(3) Linear regulators use decoupling capacitors for input and output to filter, which helps stabilize voltage and removes momentary pulse waveform interference from the power supply.

(4) The square relationship between voltage and power consumption suggests that the ideal and efficient method is to execute code at lower clock rates with lower voltage requirements, rather than executing code at the highest clock rate and then switching to idle sleep.

(5) The power supply is generally regarded as the “heart” of the entire system, with 50% to 80% of the energy-saving potential in most electronic devices lying in the power supply system; developing new types of switching power supplies is one of the main measures for energy saving.

(6) Design techniques for reducing power consumption:

• A. Use low-power devices, such as selecting CMOS circuit chips.

• B. Use highly integrated dedicated devices, and external devices should also support low-power design whenever possible.

• C. Dynamically adjust the processor’s clock frequency and voltage, using low-frequency devices whenever possible.

• D. Utilize “power-saving” operating modes.

• E. Properly handle unused pins of devices:

1. a. The output of most digital circuits has much higher power consumption when outputting low levels than when outputting high levels; design should control the output time of low levels, keeping them in high-level output states during idle times.

2. b. Extra inputs of NAND and NOR gates should be connected to low levels, while extra inputs of AND and OR gates should be connected to high levels.

3. c. For ROM or RAM and other devices with chip select signals, do not directly connect the “chip select” pin to ground, avoiding long-term activation of the device, and instead combine it with the “read/write” signal, enabling it only during read/write operations.

• F. Implement power management by designing external device power control circuits to manage the power supply of “high power consumption” devices.

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