In the field of PCB design, electronic engineers need to create reasonable routing layouts to enhance circuit performance and stability. However, many beginners lack experience and are prone to making mistakes in routing. Therefore, this article will share ten routing rules to help you avoid interference pitfalls and create better circuit boards!
1. Area Isolation: Digital/Analog/DAA Zone Segmentation
Enforce the division of digital, analog, and DAA (Data Access) independent wiring zones, using physical spacing or ground slots for isolation, and prohibit crossing zones in routing.
2. Component Placement: Signal Type Determines Physical Coordinates
Digital ICs and high-speed devices should cluster in the digital area, while analog operational amplifiers/ADCs/DACs should be placed in the analog area, and DAA chips should be close to RJ11/RJ45 interfaces.
3. High-Speed Line Rule: 1/3 Wavelength Limit
The length of clock/bus/RF signal routing should be ≤ 1/3 of the signal wavelength (e.g., for a 100MHz signal with a wavelength of 3m, routing ≤ 1m, which translates to approximately 16cm on the PCB).
4. Sensitive Line Prohibition: Analog Signal ≤ 5cm Red Line
Audio/sensor/ADC reference voltage and other analog lines must be ≤ 5cm; if exceeded, ground shielding or serpentine routing must be added.
5. Power Distribution: Star Topology + Decoupling Matrix
Digital power should use a star topology, while analog power should be on a separate layer. Each pair of ICs should be configured with a combination of 0.1μF + 10μF tantalum capacitors, with a spacing of ≤ 1cm.
6. Grounding Strategy: Three Grounds + Single Point Convergence
DGND (Digital Ground), AGND (Analog Ground), and Chassis GND (Chassis Ground) should be independently wired and connected at a single point using a 0Ω resistor or ferrite bead.
7. Line Width Prohibition: Power/Critical Signals ≥ 15mil
The line width for key signal lines such as the main power circuit, reset line, and clock line must be ≥ 15mil (0.38mm), and vias should use double-sided pads.
8. Interface Layout: Functional Modules Positioned Nearby
Digital buses (e.g., PCIe/DDR) should be placed close to the CPU/FPGA, and DAA circuits (including transformers/ESD) should be ≤ 2cm from RJ11, with analog front ends near sensors.
9. 3W Principle: Signal Spacing Hard Indicator
The spacing between different network signal lines should be ≥ 3 times the line width (e.g., for 8mil routing, spacing should be ≥ 24mil), and the spacing within differential pairs should maintain 6mil ± 10%.
10. 45° Routing: Right Angle Prohibition + Serpentine Parameters
It is mandatory to use 45° bends, with the serpentine routing pitch for differential pairs being ≥ 3 times the line width, amplitude ≥ 1.5 times the line width, and error ≤ ±15%.
This article is an original piece by Yiy Education. Please indicate the source when reprinting!