Recently, the semiconductor company Ambarella, which focuses on AI visual perception, unveiled its latest AI domain controller chip, the CV3 series, at CES. This flagship AI domain controller boasts a computing power of up to 500 eTOPS and claims to achieve ADAS and L4-level autonomous driving capabilities with a single chip.
What does such a powerful AI chip look like? Let’s hear from Ambarella’s General Manager for China, Feng Yutao, and Vice President of Marketing for China, Qie Jianjun.
5-Nanometer Low Power Process Design
All products in the CV3 series are designed using a 5-nanometer low power process. In fact, the 5-nanometer process is not new, as the previous CV5 series products have already validated the reliability of this advanced process technology.
Computing Power Up to 500 eTOPS
The CV3 series SoC is based on the fully scalable and high energy efficiency CVflow® architecture, featuring up to 16 Arm Cortex-A78AE CPU cores. Its next-generation CVflow provides the highest AI processing performance in the automotive industry—up to 500 eTOPS, which is a 42-fold increase compared to Ambarella’s previous generation automotive-grade SoC, CV2, and a 30-fold increase in CPU performance required for autonomous driving system software applications compared to the previous generation chip CV2.
Superb Environmental Perception Capability
The CV3 integrates multiple sensors for centralized AI perception processing (including high-pixel vision processing, millimeter-wave radar, lidar, and ultrasonic radar), multi-sensor deep fusion, and path planning for autonomous vehicles, all on a single chip. These outstanding capabilities help build ADAS systems and L2+ to L4 level autonomous driving systems. Even in adverse lighting conditions, weather states, and driving conditions, the AI domain controller based on CV3 can achieve superb environmental perception capabilities.
Next-Generation CVflow Architecture
The CV3 adopts Ambarella’s next-generation CVflow architecture, which continues the algorithm-first design philosophy. The new architecture includes two modules: NVP (Neural Vector Processor) and GVP (General Vector Processor).
The enhanced NVP can run advanced neural network algorithms and radar perception algorithms, such as the Aoku 4D imaging radar AI algorithm. The new floating-point General Vector Processor (GVP) complements it by helping the NVP engine handle traditional machine vision and radar processing, as well as assisting the Arm CPU with floating-point intensive algorithms.
Although the next-generation CVflow adopts a completely new design, customers need not worry about the development environment and toolchain; algorithms running on the original CVflow architecture can be easily migrated to the new architecture.
Simultaneously Supports 20 Camera Inputs
The CV3 series is equipped with Ambarella’s latest generation ISP, continuing to leverage its leading advantages in image processing. Image processing ISP and video compression of images were the initial focus areas when Ambarella was established; we have achieved image processing and ISP to image encoding technology through our self-developed IP, with over 17 years of accumulation and technological iteration.
Thus, the CV3 can support 20 camera inputs simultaneously through MIPI VC connections, processing an entire set of sensors with just a single chip, such as a typical L2+ autonomous driving sensor configuration (e.g., 10 cameras, 5 millimeter-wave radars, and numerous ultrasonic radars).
In addition, the CV3 chip features a high-performance stereo vision engine and dense optical flow engine to provide a wider range of depth detection and motion perception.
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