In embedded systems, Cortex-M3 is a 32 bit RISC processor core designed by ARM and is widely used in low-power, real-time applications (such as IoT, industrial control, etc.). Its programming model defines the architectural features, registers, memory access, exception handling mechanisms, and other aspects that developers need to understand. Below are the core contents of the Cortex-M3 programming model:
1. Register Groups
The Cortex-M3 includes the following core registers:
1. General Purpose Registers (R0-R12)
Used for general data operations, R0-R7 can be accessed by all instructions, while R8-R12 require 32 bit instructions.
2. Stack Pointer (SP)
Divided into MSP (Main Stack Pointer) and PSP (Process Stack Pointer), switched via the CONTROL register.
MSP is used for kernel mode or exception handling, while PSP is used for user task mode.
3. Link Register (LR/R14)
Saves the function return address and automatically saves the context when an exception occurs.
4. Program Counter (PC/R15)
Points to the address of the currently executing instruction.
5. Special Registers
APSR (Application Program Status Register): Saves condition flags (such as Z, C, N, V).
IPSR (Interrupt Program Status Register): Records the current interrupt number.
EPSR (Execution Program Status Register): Contains the Thumb state bit (the Cortex-M only supports Thumb instructions).
CONTROL: Defines privilege levels (privileged / unprivileged) and stack selection (MSP/PSP).
2. Operating Modes and Privilege Levels
1. Operating Modes
Thread Mode (Thread Mode): Executes normal code (such as applications).
Handler Mode (Handler Mode): Handles exceptions or interrupts (such as Interrupt Service Routines ISR).
2. Privilege Levels
Privileged Level: Can access all resources (such as system registers, memory configurations).
Unprivileged Level: Restricted, cannot directly access sensitive resources (elevated privileges through exceptions or SVC instructions).
3. Memory Mapping
Unified Address Space: Code, data, peripherals, and system control are all mapped to a 4GB linear address space.
Key Areas:
`0x00000000`: Code Area (Flash).
`0x20000000`:SRAM Area.
`0x40000000`: Peripheral Area.
`0xE0000000`: System Control Area (NVIC, SCB , etc.).
Memory Protection Unit (MPU): An optional component used to set memory region permissions (requires privileged level configuration).
4. Exception and Interrupt Handling
1. Types of Exceptions
System Exceptions: Such as reset, NMI, hard faults, SVC calls, PendSV (for RTOS context switching), etc.
External Interrupts (IRQ): Triggered by peripherals (such as timers, UART).
2. Priority and Vector Table
Vector Table: Stored at the starting location in Flash (relocatable), contains the entry addresses of exception handling functions.
Priority: Supports configurable priorities (0 is the highest, with higher values indicating lower priority).
3. Exception Handling Process
When an exception is triggered, the processor automatically saves the context (PC, LR, PSR , etc. to the stack).
Jumps to the corresponding exception handling function in the vector table.
Exits by using `BX LR` or `POP {PC}` to restore the context.
4. Nested Vector Interrupt Controller (NVIC)
Manages interrupt enabling and priority configuration.
Supports tail chaining optimization (consecutive interrupts do not require repeated context saving).
5. Instruction Set
Thumb-2 Instruction Set: A mix of 16/32 bit instructions, balancing code density and performance.
Common Instruction Types:
Data Processing:`MOV`, `ADD`, `SUB`, `MUL`.
Memory Access:`LDR`, `STR`, `PUSH`, `POP`.
Branching:`B`, `BL`, `BX` (supports conditional branching).
System Control:`CPSID/CPSIE` (global interrupt switch), `SVC` (triggers a system call).
6. Development Tools and Programming
1. Toolchain
Compiler:ARMCC (Keil), IAR, GCC (arm-none-eabi).
Debugger:J-Link, ST-Link, supports JTAG/SWD interfaces.
2. CMSIS (Cortex Microcontroller Software Interface Standard)
Hardware abstraction layer provided by ARM, includes register definitions, startup code, and peripheral driver framework.
Simplifies code portability across chip manufacturers (such as STM32, NXP).
3. Startup Process
After reset, reads the initial MSP and PC from `0x00000000`.
Executes `Reset_Handler` to initialize `.data`, `.bss` sections, and calls `main()`.
7. Key Programming Practices
1. Interrupt Service Routines (ISR)
Use `__attribute__((interrupt))` or CMSIS standard function names (such as `void TIM2_IRQHandler(void)`.).
Must manually clear peripheral interrupt flags.
2. Privilege Level Switching
Unprivileged code triggers exceptions via `SVC` instruction to perform privileged operations in the Handler.
3. Low Power Management
Enters sleep mode using `WFI` (Wait for Interrupt) or `WFE` (Wait for Event) instructions.
8. Debugging and Troubleshooting
Hard fault handling: Analyze the stack using HardFault_Handler to locate errors in LR and PC.
Breakpoints and watchpoints: Use the debugger to set breakpoints or monitor memory changes.
The programming model of Cortex-M3 revolves around its streamlined register design, efficient exception mechanisms, and flexible memory management. Developers need to be familiar with its operating modes, interrupt handling processes, and the use of toolchains, combined with the CMSIS standard library to significantly improve development efficiency. In practical development, special attention should be paid to stack management, privilege level switching, and low-power design.