Detailed Explanation of ECC Technology in SoC

Introduction: This article summarizes the plan to add ECC support to the bus system of echo_soc.

1. Basic Principles of ECC

1.1 What is ECC

ECC, or Error Correction Code, is a key technology widely used in digital circuit systems, playing a crucial role in data storage or transmission. Its core function is to accurately detect and effectively correct single or multiple bit errors in data, thereby enhancing the reliability and robustness of the system.

In practical operation, ECC achieves this goal by cleverly adding redundant bits to the original data. When data is read at the receiving end, these redundant bits become a powerful basis for detecting and correcting errors. For example, in a simple data transmission scenario, the sender transmits the original data 1011 to the receiver, while generating redundant bits based on a specific ECC algorithm and sending them together. Upon receiving the data and redundant bits, the receiver uses the same algorithm for verification. If the data experiences a 1-bit error during transmission due to noise interference, such as changing to 1001, the receiver can accurately locate the error position using the redundant bits and verification algorithm, correcting it back to the original 1011, ensuring data accuracy.

1.2 Key Objectives of ECC

Detecting Errors: The primary goal of ECC is to sensitively determine whether the received data matches the data sent by the sender. In complex data transmission and storage environments, data is easily affected by various interferences, such as electromagnetic interference and hardware failures, leading to bit flips. ECC can quickly detect these changes through its unique verification mechanism, and once data inconsistency is detected, it immediately triggers subsequent error correction processes.
Correcting Errors: For a certain number of bit errors, ECC has a powerful ability to recover the correct data content. Taking the common 1-bit error as an example, ECC can accurately locate the error position and correct it based on the information provided by the redundant bits. For multiple bit errors, some advanced ECC algorithms can also effectively repair within a certain range, maximizing data integrity and accuracy.
Fault-Tolerant Design: From a system perspective, ECC is a key component in ensuring data integrity, especially excelling in addressing soft errors. Soft errors are typically caused by external factors such as alpha particles or cosmic rays. With the continuous evolution of integrated circuit manufacturing processes, the charge levels in internal storage units like SRAM and Flash are decreasing, significantly increasing sensitivity to such soft errors. The application of ECC technology can greatly reduce functional anomalies caused by bit flips, effectively lowering system failure rates and ensuring stable and reliable operation in complex environments.

1.3 Application Background of ECC

In the SoC (System on Chip) field, as manufacturing processes advance towards finer resolutions, SRAM, Flash, and other memory types face severe challenges. Due to the reduction in charge levels in storage units, their resistance to interference weakens, and the system’s sensitivity to soft errors increases dramatically. For instance, in automotive electronics and aerospace applications where reliability is paramount, even a tiny bit flip can lead to severe consequences.

In the electronic control systems of vehicles, the Engine Control Unit (ECU) needs to accurately read and process sensor data. If the SRAM storing this data experiences a bit flip, it may lead to incorrect control command outputs, affecting the normal operation of the engine and even jeopardizing driving safety. The introduction of ECC technology can promptly detect and correct these errors, significantly enhancing system reliability and effectively reducing the risk of system failures due to soft errors, providing a solid guarantee for the stable operation of SoC in complex environments.

2. Common ECC Algorithms and Their Advantages and Disadvantages

2.1 Parity Check

Characteristics: The parity check algorithm has the significant advantage of low unit cost, and its implementation is relatively simple, requiring only the addition of a parity bit to the data. By counting the number of 1s in the data, if odd parity is used, the total number of 1s including the parity bit will be odd; if even parity is used, the total number of 1s will be even. However, the limitations of parity check are also quite obvious; it can only detect odd-numbered bit flips and is powerless against even-numbered errors, and it has no error correction capability.
Usage Scenarios: Due to its low cost and simple detection characteristics, parity check is commonly used in cost-sensitive scenarios with low error detection requirements, such as I/O bus checks and FIFO checks. In these scenarios, parity check can quickly detect some errors, providing a basic level of assurance for the system.

2.2 Hamming Code

Characteristics: Hamming code is the most commonly used 1-bit error correction and 2-bit detection mechanism (SEC-DED), offering an excellent cost-performance ratio. It introduces minimal delay during encoding and decoding, making it suitable for high-speed paths. In calculating redundant bits, for k bits of data, r redundant bits are required, satisfying the formula 2^r ≥ k + r + 1. For example, for 8 bits of data, this formula indicates that 4 redundant bits are needed to achieve effective verification and correction of the data.
Usage Scenarios: Hamming code is widely used in critical paths such as SRAM and Cache. These scenarios require high data accuracy and transmission speed, and Hamming code can effectively detect and correct errors while ensuring high-speed operation, ensuring reliable read and write of data.

2.3 BCH Code (Bose-Chaudhuri-Hocquenghem)

Characteristics: BCH code has powerful multi-bit error correction capabilities (t-bit correction) and can handle more complex error situations, providing high reliability for data. However, its encoding complexity and decoding delay are relatively high due to its complex mathematical operations. In practical applications, a balance must be struck between its high reliability and high complexity.
Usage Scenarios: In NAND Flash controllers and memory systems where data reliability is extremely critical, BCH code plays an important role. The storage characteristics of NAND Flash make it prone to multi-bit errors during use, and BCH code can effectively correct these errors, ensuring data integrity.

2.4 Reed-Solomon Code

Characteristics: Reed-Solomon code is widely used for correcting burst errors and performs excellently in serial data transmission scenarios. It can effectively handle situations where multiple consecutive bits are erroneous. However, its encoding and decoding complexity is high, requiring significant computational resources.
Usage Scenarios: Reed-Solomon code is extensively applied in communication systems, optical discs, Ethernet, Flash controllers, etc. For example, in optical disc storage, data may be affected by scratches, dust, and other factors during reading, leading to burst errors. Reed-Solomon code can effectively correct these errors, ensuring correct data reading.

2.5 CRC (Cyclic Redundancy Check)

Characteristics: CRC has powerful error detection capabilities, verifying data by generating a fixed-length checksum. Its implementation is relatively simple, and various polynomials are available for different application scenarios to meet diverse needs. However, CRC does not have error correction capabilities; it can only detect whether errors exist in the data, and once an error is detected, it must be resolved through retransmission or other means.
Usage Scenarios: CRC is widely used in transmission paths, interface protocols, and other scenarios, such as CAN, SPI, USB, and other peripheral interfaces. In these interface communications, CRC can quickly detect whether data has errors during transmission, ensuring the accuracy of data communication.

2.6 SEC-DED-DA (Double Adjacent)

Characteristics: SEC-DED-DA enhances the original SEC-DED by adding the ability to detect two adjacent bit errors. This feature allows it to better address coupling flip issues in SRAM, further improving data reliability. In applications where data accuracy is critical, this capability to detect adjacent bit errors is particularly important.
Usage Scenarios: SEC-DED-DA is applied in storage devices like SRAM, where coupling flips are likely to occur. By detecting and handling adjacent bit errors, it can effectively reduce errors caused by the physical characteristics of storage devices, ensuring stable system operation.

3. Typical Application Locations of ECC in SoC

The deployment of ECC in SoC is a complex system engineering task that requires comprehensive consideration of fault modes, performance requirements, power budget, area overhead, and other factors to achieve optimal system design. The following are the main application locations of ECC in SoC:

3.1 On-chip SRAM

ECC Configuration: Typically, SEC-DED ECC is used, which can effectively detect and correct single-bit errors while detecting double-bit errors.
Port Support: Multi-port support allows for parallel encoding and decoding, significantly improving data processing speed. In high-speed data read/write scenarios, parallel processing capabilities can fully leverage the performance advantages of SRAM, reducing data access latency.
Latency Optimization: Since SRAM is in a high-speed path and is very sensitive to latency, Pipeline ECC or embedded ECC support is required. Pipeline ECC decomposes the encoding and decoding processes into multiple stages through a pipeline design, improving processing efficiency without adding extra latency; embedded ECC integrates ECC functionality into SRAM, further reducing data transmission latency, ensuring the system meets high-speed operation requirements.

3.2 Cache (L1 / L2 / L3)

L1 Cache: L1 typically does not have ECC, only using Parity or RAZWI (Random-Access Zero-Wait-State Memory with Inversion). This is because L1 Cache has extremely high speed requirements, and the introduction of ECC may add extra latency, affecting cache hit performance. Parity or RAZWI can provide a certain level of error detection without significantly impacting speed.
L2/L3 Cache: L2/L3 can use SEC-DED or stronger error correction (such as BCH). Compared to L1 Cache, L2/L3 Cache has relatively lower speed requirements but higher data reliability requirements. Using stronger ECC algorithms can effectively ensure data accuracy without significantly impacting overall system performance.
Performance Assurance: Regardless of the ECC configuration used, it is essential to ensure that ECC protection does not affect cache hit performance. During the design process, careful optimization of the collaboration between ECC algorithms and cache architecture is required, using reasonable caching strategies and data layouts to minimize the impact of ECC verification on cache access speed.

3.3 TCM (Tightly Coupled Memory)

Functional Requirements: TCM, as a dedicated high-speed memory for CPUs, is often used in automotive MCUs, requiring extremely high reliability. It must have 1-bit error correction + 2-bit detection capabilities to ensure accurate read and write of data in complex automotive electronic environments. Additionally, it should support real-time refresh and error correction functions to promptly detect and handle data errors, ensuring continuous stable operation of the system.
Self-Test Function: In some architectures, TCM supports Error Injection for self-testing. By actively injecting error signals, the system can periodically test and verify the ECC functionality, ensuring that ECC operates correctly during actual operation. This self-test mechanism is crucial for ensuring the safety and reliability of automotive MCUs.

3.4 eFlash/eEEPROM Controllers

Error Correction Algorithm: Using BCH/Reed-Solomon codes for page-level error correction. eFlash and eEEPROM are prone to multi-bit errors and burst errors during data storage due to their physical characteristics. BCH/Reed-Solomon codes can effectively handle these complex error situations, ensuring data integrity.
Dynamic Adjustment: Supports dynamic error correction levels (based on aging). As eFlash and eEEPROM age, their storage performance gradually declines, and the probability of errors increases. By dynamically adjusting the error correction level, the system can flexibly adjust the strength of the ECC algorithm based on the actual aging condition of the storage device, ensuring reliable data storage services throughout the device’s lifecycle.

3.5 DMA and Bus Interfaces

Transmission Verification: When transmitting between AXI, AHB, and APB buses, add ECC or Parity checks. Data during bus transmission is susceptible to electromagnetic interference and other factors, leading to errors. By adding ECC or Parity checks, the accuracy of data transmission can be monitored in real-time, and once an error is detected, timely retransmission measures can be taken to ensure data transmission reliability.
Error Identification: The AXI-4 specification recommends using the EEC (Error Encoding and Checking) signal domain to indicate bit errors. The EEC signal domain can clearly identify the type and location of errors, facilitating system error diagnosis and processing, improving system maintainability.

3.6 CPU Internal Register Files / Execution Units

High Reliability Requirements: In high-reliability systems (such as ISO 26262 ASIL-D), critical registers are protected by ECC. These critical registers store important parameters and instructions for system operation, and any errors could lead to system failures. ECC protection ensures the accuracy of register data, enhancing system reliability and safety.
Architecture Support: Some RISC-V cores or ARM Cortex-R architectures support ECC register paths. This architectural support allows ECC to be applied more efficiently within the CPU, providing reliable error detection and correction functionality for critical registers without affecting CPU operating speed.

4. Requirements and Applications of ECC in Automotive-grade MCUs

Automotive-grade SoC or MCU systems, especially those meeting ISO 26262 ASIL-B/C/D levels, have extremely stringent requirements for ECC to ensure that the system maintains a high level of functional safety in complex and variable electrical or radiation interference environments.

4.1 ECC Requirements Corresponding to Safety Levels

ASIL-B: For ASIL-B level, the requirement is to be able to detect errors, typically using Parity checks. Parity checks can detect errors in data to a certain extent, meeting the basic requirements for error detection at ASIL-B, and their implementation cost is low, not placing too much burden on the system.
ASIL-C: ASIL-C level requires 1-bit error correction (SEC) capability. In automotive electronic systems, errors in critical data can lead to severe consequences, and 1-bit error correction capability can promptly correct single-bit errors, effectively improving data accuracy and system reliability, ensuring the system can operate normally in the face of a certain degree of interference.
ASIL-D: ASIL-D, as the highest safety level, requires 1-bit error correction + multi-bit detection (SEC-DED-DA or BCH) capability. Under such high requirements, SEC-DED-DA or BCH algorithms can handle more complex error situations, including single-bit errors, multi-bit errors, and adjacent bit errors, providing comprehensive data protection for the system and maximizing functional safety.

4.2 Safety Mechanisms Combined with ECC

Memory BIST + ECC: Memory BIST (Built-In Self-Test) combined with runtime error correction ECC can comprehensively ensure the reliability of memory. During the power-on phase, Memory BIST conducts comprehensive testing of the memory to identify potential faults; during system operation, ECC monitors and corrects data errors in real-time. The combination of the two ensures stable operation of the memory throughout its lifecycle.
Redundancy + ECC: Dual-core lockstep combined with ECC protection for TCM is a common redundancy design scheme. Dual-core lockstep synchronously executes the same instructions on two cores and compares execution results in real-time. Once a difference is detected, a safety mechanism is triggered; ECC detects and corrects errors in the data within TCM, further enhancing data reliability. This combination of redundancy design and ECC can effectively reduce the risk of system failure due to hardware faults or data errors.
Error Injection Mechanism: Supports software injection of bit errors to verify ECC functionality. By actively injecting errors during system operation, the ECC detection and correction capabilities can be periodically tested, ensuring that ECC operates correctly in practical applications. This error injection mechanism is one of the important means to ensure functional safety of the system.
Error Response Strategies: Supports ECC error interrupts, NMI (Non-Maskable Interrupt), hardware reset, and other actions. When ECC detects an error, the system can take corresponding response strategies based on the severity of the error. For minor errors, software can be notified via interrupts for processing; for severe errors, NMI or hardware reset is immediately triggered to ensure the system enters a safe state, avoiding more serious consequences due to error accumulation.

4.3 Typical Application Modules

Safety Monitoring Core (Safety CPU): The safety monitoring core is a key module in automotive-grade MCUs, responsible for real-time monitoring of the system’s operational status, with extremely high requirements for data accuracy and reliability. The application of ECC technology can ensure that the data obtained by the safety monitoring core is accurate, promptly detecting and handling anomalies in the system, providing assurance for the safe operation of the entire system.
PWM Control Registers: PWM control registers are used for precise control of devices such as motors and lights. In automotive electronic systems, the accuracy of PWM control directly affects the performance and safety of the devices. ECC protection can prevent data in PWM control registers from being erroneous due to interference, ensuring the stability and accuracy of PWM outputs, safeguarding the normal operation of related devices.
Message Buffers of CAN FD Controllers: CAN FD (Controller Area Network with Flexible Data-Rate) is a widely used communication protocol in automotive electronics, and its controller’s message buffers require reliable data storage. ECC can detect and correct errors in the message buffers, ensuring the reliability of CAN FD communication and preventing communication failures due to data errors, ensuring effective communication between various nodes in automotive electronic systems.
TCM/Flash/EEPROM and Other Major Storage Paths: These major storage paths store the program code and important data required for system operation. The application of ECC in these storage paths can effectively protect data integrity, preventing data loss or errors caused by storage device failures or external interference, ensuring stable operation of the system under various conditions. For example, during vehicle operation, strong electromagnetic interference may occur, and ECC can ensure that the data stored in these devices is unaffected, maintaining normal system operation.