Coresight has two main functions: debugging and tracing.
1. Debugging
The debugger implements debugging functionality through DAP.
1.1. Single-Core Debugging System:
One DAP, along with one AP and APBIC. External access to the DP is transformed by the DAP into AP access. The AP generates the AP bus through the APBIC, allowing access to debugging resources within the ARM core or to Coresight components connected to the debug APB.
1.2. Multi-Core Debugging System:
One DAP, which implements multiple APs internally. These APs access debugging resources via JTAG or memory-mapped methods.
External access to the DP is transformed by the DAP into APB AP or JTAG AP access. If it is JTAG access, it directly accesses the processor connected to the JTAG via the JTAG AP. If it is APB access, the APX mux determines whether to access the processor or the Coresight components connected to the debug APB. If accessing the processor, it goes through the APB bridge. If accessing the Coresight components, it accesses them directly.
The following diagram shows the position of the debug components within the Coresight system.
2. Tracing
2.1. Simple Single-Core Tracing System
The following diagram shows a simple single-core tracing system with only one trace source.
There is only one trace source (ETM), so no trace link components are needed in between. The trace source directly outputs trace information to the trace sink (TPIU). Since there is only one trace source, trace formatters are also unnecessary.
2.2. Advanced Single-Core Tracing System
The following diagram shows an advanced single-core tracing system with multiple trace sources.
With multiple trace sources (ETM, STM), trace link components (funnel) are required to merge trace information and send it to replicators, which then distribute it to trace sinks (TPIU, ETB). Because there are trace link components, the trace sink requires trace formatters to format the trace data and obtain the actual data.
2.3. Advanced Multi-Core Tracing System
There are multiple cores, each with its own trace components. Therefore, it will include many Coresight components with tracing functionalities.
3. Complete Coresight System with Multiple Clusters
The following diagram shows a complete Coresight system with multiple clusters.
The system contains two clusters:
-
System 1, with a processor as the main device. This system includes multiple Coresight components: debug components, trace components, and trigger components.
-
System 2, with a DSP as the main device. This system also includes multiple Coresight components: debug components, trace components, and trigger components.
The two subsystems are connected through an interconnect, enabling communication and access to external peripherals. At the same time, the CTM of both subsystems is connected to an external CTM, allowing for event transmission between the two subsystems.
The entire system includes one DAP, which contains a DP, SWJ-DP (JTAG and SW protocol conversion), and two APs: AHB-AP (generating AHB bus) and APB-AP (generating APB bus).
The AHB bus generated by the AHB-AP is directly connected to the interconnect in the system, allowing access to external peripherals (such as memory) connected to the interconnect.
The APB bus generated by the APB-AP connects to the debug APB of both subsystems, enabling register access to the Coresight components of the subsystems, such as ETM, CTI, HTM, funnel, etc. Additionally, the APB bus connects to the system’s debug APB, allowing register access to the system’s Coresight components, such as funnel, ETB, TPIU, CTI, etc.
The trace information from both subsystems is output through their respective funnels to the system’s funnel, which merges the trace information from both subsystems and then outputs it to the replicator. The replicator broadcasts the received trace information to the ETB and TPIU. The TPIU outputs the information to the outside through the trace port.
