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Currently, among the controllers responsible for core vehicle control functions, a significant portion of the processors used are based on the ARM architecture. This architecture holds a crucial position in the automotive electronics field due to its excellent energy efficiency, extensive ecosystem support, and high flexibility. Therefore, this article aims to briefly introduce the characteristics of ARM architecture processors for discussion and exchange.
ARM is a company based in the UK that designed the first low-power cost RISC microprocessor, namely the ARM processor (Advanced RISC Machines). After the classic processor ARM11, ARM’s products began to adopt the Cortex naming convention and were divided into A, R, and M categories to serve various markets. The Cortex series belongs to the ARMv7 architecture, which was the latest instruction set architecture from ARM at that time. Therefore, it can be said that Cortex is the name of a series of processors launched by ARM, with origins tracing back to ARM’s processor design and development history.
First, let’s briefly explain the concept of the instruction set of a chip processor. The instruction set mainly refers to the interface description between the CPU hardware and software, which is essentially a segment of binary machine code. The CPU can only recognize and execute these machine code instructions, while the machine code itself is a string of meaningless characters, making it difficult for programmers to understand and use. Therefore, high-level programming languages such as assembly language were invented, which have a one-to-one correspondence with machine code, allowing programmers to write and debug programs more easily.
Instruction sets can be divided into various types, among which the most famous are Complex Instruction Set (CISC) and Reduced Instruction Set (RISC).
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Complex Instruction Set (CISC):This type of instruction set contains a large number of instructions, and each instruction has a relatively complex function. The X86 instruction set is a typical example of a CISC instruction set.
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Reduced Instruction Set (RISC):In contrast to CISC, RISC instruction sets contain fewer instructions, and each instruction has a relatively simple function. The ARM instruction set is a representative of RISC instruction sets, widely used in mobile devices, embedded systems, and other fields.
We often hear terms like “ARM architecture chips,” which actually refer to the specific instruction set used by a certain processor. Currently, the mainstream chip architectures in the market include X86, ARM, RISC-V, and MIPS.
In most cases, architecture equals instruction set. For example, if a processor is based on the ARMv7 architecture, it uses the ARMv7 instruction set. The instruction set architecture is part of the computer architecture, defining the set of instructions that the processor can recognize and execute. The ARM architecture also has v8 and v9 versions, with v7 being an earlier version that is widely used today. The ARMv7 architecture is divided into A series (Application Processors for high-performance products), R series (Real-time Processors for real-time systems), and M series (Microcontroller Processors for microcontrollers); ARMv9 is the latest version of the ARM architecture. The comparison of the instruction sets across these three versions is roughly as follows:
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It introduces a new instruction set, such as Thumb-2, which is a new instruction set that mixes 32-bit and 16-bit instructions, providing high performance while saving storage space.
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ARMv7 also supports hardware floating-point operations (VFPv3), enhancing the processor’s ability to handle floating-point numbers.
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This is the first 64-bit architecture version introduced by ARM.
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It supports both 64-bit and 32-bit applications, providing a larger address space, more registers, and enhanced security features.
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ARMv8 introduces a new instruction set AArch64 for executing 64-bit operations.
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This architecture also improves support for floating-point and SIMD (Single Instruction Multiple Data), including new floating-point operation instructions and new SIMD instructions optimized for multimedia and data processing.
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ARMv8 also introduces hardware virtualization support, improving the performance of applications running in virtual environments.
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ARMv9 introduces a series of optimizations and improvements over previous versions to enhance processor performance and efficiency.
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It introduces new SVE2 (Scalable Vector Extension 2) technology, a vector operation technology that can significantly improve the processor’s ability to handle machine learning and artificial intelligence tasks.
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ARMv9 also enhances security features, introducing a new Realm management architecture to more effectively prevent various cyberattacks and data leaks.
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This architecture improves virtualization support, making virtualization more efficient in cloud computing and other high-performance computing applications.
Simply put, the instruction set is the bridge between the CPU and software, enabling software to correctly control the CPU to perform various operations. At the same time, the instruction set also determines key indicators such as CPU performance and power consumption. Different instruction sets have different characteristics and advantages, making them suitable for various application scenarios.
Application of Cortex Cores in Automotive Chips
The ARM Cortex series chips commonly used in vehicle controllers generally belong to the ARMv7 and v8 architectures.
ARM Cortex series chips are divided into A, R, and M series, which is also the origin of the chip A-core and M-core terms we often hear.
Cortex-A is a high-end processor aimed at markets such as mobile computing, smartphones, and servers, with high operating frequencies (>1GHz) and supporting memory management units required by operating systems such as Linux, Android, and Windows. In the automotive field, it can be used for cockpit chips, intelligent driving chips, central computing platform chips, etc.
Cortex-R is used for real-time applications, such as body controllers, automotive chassis systems, and power system control, without supporting memory management units but possessing other storage functions, operating at high frequencies (200MHz to >1GHz) with low response latency, supporting real-time operating systems rather than full Linux and Windows.
Cortex-M is designed to be compact and energy-efficient, with lower clock frequencies but some reaching over 200MHz. The new Cortex-M series is easy to use and is widely popular in microcontrollers and deep embedded systems, and can also be used for body control, although its performance is slightly inferior to Cortex-R.
The chip architecture of Xinchi X9 series
The main processors of the G9 series gateway chips, V9 series intelligent driving chips, and X9 series cockpit chips from the domestic chip manufacturer Xinchi are primarily in the form of Cortex-A55 + Cortex-R5, forming a multi-core heterogeneous chip.
The chip architecture of Xinchi E3 series
However, the main chips of Xinchi designed for vehicle control and domain control, the E3 series, do not adopt Cortex-A but are in the form of Cortex-R5 and Cortex-R52+, as the E3 MCU is a new generation of high-performance microcontroller products designed for automotive safety-related applications. Based on this requirement, Cortex-A was not chosen, but the real-time and high-security Cortex-R series processors were selected.
NXP S32G399A Architecture Diagram
For example, NXP’s domain control and gateway series products, the S32G series, choose a processor core in the form of Cortex-M7 + Cortex-A53, with the highest-end product S32G399A having 4 Cortex-M7 + 8 Cortex-A53, this heterogeneous form allows the entire SoC to have high computing power while also meeting ASIL D safety standards on Cortex-M.
S32K3 Series Processor Composition
In addition, NXP’s S32K3 series chips are widely used in power management, inverter control, body area control, and other areas, and this series has multiple Cortex-M7 cores, some of which also have two lock-step Cortex-M7 cores. Dual Core Lock Step (DCLS) is a CPU redundancy technology that includes two identical processors within a chip. These two processors operate in a master-slave relationship, executing the same code and strictly synchronizing. Importantly, the dual-core lock-step technology can quickly detect and isolate processor operation errors through hardware-level redundancy and comparison mechanisms, preventing fault propagation.
S32K39x (x=4 or 6) Chip Block Diagram
Renesas’ MCU/MPU/SoC products also widely use ARM architecture cores.
Renesas’ R-Car H3e Architecture
Renesas’ R-Car H3e (-2G) is a high-end computing automotive SoC, with core processors including four Cortex-A57, four Cortex-A53, and dual-core lock-step Cortex-R7, providing powerful computing performance to accurately and in real-time process large amounts of information from automotive sensors. Its applications are very broad, such as in-car entertainment information systems and integrated cockpits. It meets ISO 26262 (ASIL-B) automotive functional safety standards and information security requirements. The (H3e-2G) operating at 2GHz maintains hardware and software compatibility while enhancing processing capabilities.
In summary, the ARM architecture plays an important role in the automotive electronics field due to its low power consumption, high performance, and customizability. With continuous technological advancements and innovations, the ARM architecture still has significant development potential. By selecting appropriate cores, optimizing code, using hardware acceleration, and optimizing memory access strategies, system performance and power efficiency can be further improved to meet the demands of various application scenarios.
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