In recent years, driven by generative AI, the RISC-V chip market has rapidly developed. According to predictions from The SHD Group, by 2030, the shipment of RISC-V SoCs is expected to reach 16.181 billion units, generating revenue of $92.7 billion; among these, the AI accelerator sector will become the fastest-growing sub-market, with an expected shipment of 4.1 billion units and revenue of $42.2 billion. Behind this trend is the explosive demand for computing power from large models, as well as the high compatibility of heterogeneous computing paradigms with RISC-V’s modular and scalable technology.
“There has always been an impossible triangle in the CPU world: autonomy and control, technological prosperity, and commercial success, which are difficult to achieve simultaneously. However, RISC-V has made it possible for these three to coexist for the first time.” On July 17, during the 2025 RISC-V China Summit held in Shanghai, the host and summit chairman, Dai Weimin, mentioned this in his opening remarks at a roundtable discussion themed “Opportunities and Challenges in the RISC-V Industry Implementation.” This discussion brought together leading experts, corporate representatives, and academic institution heads from the RISC-V field, focusing on four core topics: AI computing power innovation, ultra-low power scenario implementation, automotive chip ecosystem construction, and toolchain maturity, revealing the strategic value and ecological potential of RISC-V in the wave of generative AI.
Host: Summit Chairman, Chairman of the Shanghai Open Processor Industry Innovation Center, Dai Weimin
Guests (listed in alphabetical order by surname):
Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences, Secretary-General of the China Open Instruction Ecosystem (RISC-V) Alliance, Chief Scientist of the Beijing Open Source Chip Research Institute, Bao Yungang;
Senior Vice President of SuanNeng, Gao Peng;
CTO of Hejian Technology, He Peixin;
Senior Vice President and CTO of Yiswei Computing, He Yu;
Founder of Chiplet Technology, Hu Zhenbo;
Chief Architect of Tenstorrent, Wei-Han Lien;
CEO of Zhihe Computing, Meng Jianyi;
Deputy General Manager of ZTE Microelectronics, Shi Yijun;
Executive Vice President and General Manager of the Custom Chip Platform Division of Chipone, Wang Zhiwei;
Vice President of Alibaba DAMO Academy, RISC, Yang Jing;
Director and Board Member of Nanjing Qinheng Microelectronics, Yang Yong;
Technical Executive Director of Synopsys, Zhang Chunlin
Dai Weimin pointed out that by 2030, the global semiconductor market size will exceed one trillion dollars, with 70% of it related to AI. He used the metaphor of “trunk-branches-leaves” to describe the migration of AI computing power—training is the trunk, edge fine-tuning is the branches, and inference cards are the leaves that are about to burst forth. Last year’s explosive “hundred model war” saw AI giants putting almost all the Nvidia GPUs they bought into the “cloud,” but in the future, we believe that more computing power will extend to the edge.
Currently, AI chips are mainly divided into two types—GPGPU and ASIC, and almost all large models are still based on the Transformer architecture. Given Nvidia’s monopoly in the GPGPU field, most startup AI chip companies generally choose to start with ASICs, optimizing for Transformers. One such company is Etched AI, founded in 2022 by Harvard University students Chris Zhu and Gavin Uberti, which has completed $120 million in Series A financing and launched the world’s first ASIC chip dedicated to Transformers, named “Sohu”.
Chris Zhu (right) and Gavin Uberti
According to Dai Weimin, “Sohu” uses TSMC’s 4nm process and is equipped with 144GB of HBM3E high-bandwidth memory, with inference performance 20 times faster than Nvidia’s H100, and its energy efficiency significantly surpasses that of traditional GPUs. However, its most distinctive feature is that it hardens the optimization for the Transformer architecture into the chip, not supporting most AI architectures such as CNN, RNN, or LSTM.
Tenstorrent, founded by chip guru Jim Keller, known as the “Silicon Wizard,” after leaving Intel, is also not taking the GPGPU route. The company specializes in designing high-performance RISC-V CPUs. Currently, it has launched a RISC-V CPU based on its own Ascalon processor core, which leads in the SPEC CPU 2017 INT Rate benchmark test for integer performance, surpassing Intel’s Sapphire Rapids (7.45 points), Nvidia’s Grace (7.44 points), and AMD’s Zen 4 (6.80 points); only trailing behind AMD’s Zen 5 (expected to reach 8.84 points, becoming the absolute integer performance champion for 2024-2025).
What is “Baby RISC-V”?
The complex control unit of traditional GPUs occupies 40% of the chip area, while “Tenstorrent’s most distinctive feature is the use of the ‘Baby RISC-V’ concept, which consists of a large number of small RISC-V cores instead of using GPGPU for AI.” Dai Weimin pointed out that this approach greatly compresses the area of the control unit, “So what exactly is Baby RISC-V?”
Tenstorrent’s Chief Architect Wei-Han Lien stated, “Cloud chips are extremely complex for generality, while accelerators focus on a specific computation. We use a large number of extremely simple RISC-V small cores—Baby RISC-V—to control data flow and computation scheduling. They only handle specialized tasks like ‘when to move data and what instructions to use,’ which are small in area, low in power consumption, and easy to optimize, yet can be more efficient than large cores in large-scale parallelism.”
Therefore, by definition, “Baby RISC-V is an extremely simple core designed specifically for AI acceleration, with each core requiring only 1000 logic gates to complete data scheduling. In the Blackhole chip, 752 Baby cores work in conjunction with 16 large cores to achieve 745 TOPS of computing power, with an energy efficiency ratio of 35 TOPS/W, surpassing the A100.” Wei-Han Lien added that this small core specialization design is an architecture composed of a large number of small-scale, specialized instruction cores, which solves the “memory wall” problem of the traditional von Neumann architecture in AI workloads, making it suitable for data flow-driven AI acceleration, highly flexible, and adaptable to various scenarios from edge-side inference to cloud training.
Zhihe Computing CEO Meng Jianyi added from an ecological perspective, “Baby RISC-V is not the only path, but it is one of the optimal solutions for compute-intensive workloads. It saves silicon area to stack computing units, bringing ‘computation’ closer to ‘business,’ suitable for heavy computation workloads.” He believes that the core value of Baby RISC-V lies in decoupling computation from control. For example, the XuanTie C930 reduces the area of the control path by 60%, increasing the computing density to 128 TOPS/mm², supporting 40 TOPS@INT8 for edge AI inference.
Meng Jianyi further pointed out that the openness of RISC-V provides a unified software interface for AI chip design, supporting both the lightweight innovation of “Baby RISC-V” and the application of “Big RISC-V” in high-performance scenarios. The open interface of RISC-V allows different devices to fit under the same shell, thus promoting ecological prosperity. “There are many paths, and everyone can try; this is healthy competition.”
Will architecture-optimized ASIC replace GPUs?
When discussing the issue of architectural choice, Shi Yijun, Deputy General Manager of ZTE Microelectronics, believes it should be viewed in terms of scenarios, reminding the industry not to be blinded by the training scenario. “The training side focuses on model capability, while the inference side is suitable for ASIC innovation. Once the models converge to a few, the energy efficiency issue will become prominent.” He pointed out that GPUs have a lot of existing work in optimization, and new architectures need to avoid these and grasp the optimization time window and ecology to iterate. There are many architectural innovation opportunities for inference-side ASICs, whether for edge, side, or cloud inference, and the openness and customizability of RISC-V can provide more choices, leading to continuous innovation in this field in the future.
Today, the RISC-V ecosystem is flourishing, with everyone competing to unknowingly enrich the ecosystem. Currently, the largest player in China is Alibaba DAMO Academy’s “XuanTie.” As a veteran in the industry who has worked at Nvidia for many years, Yang Jing, Vice President of Alibaba DAMO Academy, approached the issue from the software ecosystem perspective, believing that “hardware innovation is only the first half; the real moat of Nvidia is the CUDA ecosystem. Chip iterations are slow, while algorithm iterations are fast, and the general GPU + CUDA solves this contradiction. The most challenging aspect for RISC-V right now is to either bring over the CUDA ecosystem or rebuild an efficient deployment method; the software stack is the long-term winning hand.”
Yang Jing revealed that the DAMO Academy’s “XuanTie” layout has chosen to support a solution with independent registers to meet the needs of large models and high computing power scenarios, while also investing heavily in software stack compatibility, “running XuanTie instances in more frameworks to allow developers to migrate painlessly.”
The audience’s voting results: Will architecture-optimized ASICs for AI and parallel computing replace GPUs and become the trend for the development of future AI training/fine-tuning/inference chips? (Single choice)
Regarding this voting result, Gao Peng, Senior Vice President of SuanNeng, stated, “It’s almost a 50-50 split, indicating that the situation is still undecided. AI’s appetite for computing power, memory, and interconnect far exceeds that of other applications, so everyone is trying new tricks like data flow, in-memory computing, and Chiplet.”
SuanNeng aims to lower the design threshold for AI chips through modular instruction set expansion and open-source IP sharing, predicting that a consensus software stack similar to CUDA may form in the future.
Gao Peng further pointed out that AI computing demands for computing power, storage, and other needs far exceed those of general applications, and the openness of RISC-V provides a carrier for related technological innovations, which Arm and x86 do not possess. Its scalability and modularity can build extended instruction sets for AI, achieving optimal chip design costs. Moreover, RISC-V has the opportunity to challenge the CUDA ecosystem, as its openness and scalability provide a foundation for innovation. Once a consensus is formed in conjunction with international foundation standards, it can gather developers.
What advantages does RISC-V have in generative AI?
According to The SHD Group’s prediction of the RISC-V market share in 2030, wearable and consumer electronics AI acceleration will account for the highest proportion. Dai Weimin believes that, in addition to these two fields, whether AI can disrupt education and healthcare in the future is also crucial. “If we want to test the chip’s capabilities, then AI/AR glasses will be a battleground for future smart hardware. At the same time, these wearable devices are also where small models will thrive, as people are increasingly concerned about privacy, and data from wearable devices generally tends not to be considered for cloud storage.”
Currently, in the field of generative AI small models, China is leading the way. Dai Weimin cited an example where Microsoft defined that the computing power of an AI PC should not be less than 40 TOPS, “but we (Chinese manufacturers) have directly integrated 40 TOPS into mobile phones (Xiaomi Xuanjie O1).”
So why is AI a new opportunity for RISC-V?
Bao Yungang, Deputy Director of the Institute of Computing Technology, Chinese Academy of Sciences, Secretary-General of the China Open Instruction Ecosystem (RISC-V) Alliance, and Chief Scientist of the Beijing Open Source Chip Research Institute, believes there are three reasons:
First, it can better collaborate with CPUs. Historically, floating-point and multimedia instructions have ultimately merged into CPUs (e.g., x86 merging floating-point units), and the trend is for AI extension instructions to combine with CPUs, facilitating cross-model calls;
Second, it is flexible and customizable. In scenarios where inference demands are diverse, the cloud needs to be fully powered, while the edge needs to be distilled. RISC-V can be tailored and optimized at the hardware level;
Third, it is conducive to unifying the software stack. Today, various AI chip companies in China are building their own silos, while RISC-V can link global forces to build a software stack ecosystem through a unified extended instruction set standard (e.g., Triton library compatibility), allowing compilers, libraries, and frameworks to share, creating an opportunity to compete with CUDA through global collaboration.
On-site audience voting results: What technical advantages does RISC-V have in enhancing the performance and efficiency of generative AI algorithms? (Select three options)
Future applications of RISC-V-based MCUs and MPUs in the next two years
While the momentum is impressive, the implementation is also a key consideration for manufacturers, as sustainable revenue generation is essential for continuous iteration.
Wang Zhiwei, Executive Vice President and General Manager of the Custom Chip Platform Division of Chipone, considers that for “always-on, ultra-low power” applications, related products are mostly electronic, and believes that RISC-V’s choice of landing areas should consider low power consumption, cost, and software maturity. “Smart home appliances (such as vacuum robots), smart watches and bands, and civilian security devices (battery-powered smart cameras) have matured in the market, and Chipone already has customers with RISC-V solutions implemented. AI/AR/VR glasses and other fields are also under development and will land quickly in the future.”
Wang Zhiwei, Executive Vice President and General Manager of the Custom Chip Platform Division of Chipone
The audience’s voting results: What are the application areas for RISC-V-based MCUs and MPUs that will land first in the next two years, focusing on always-on, ultra-low energy, and ultra-lightweight applications?
“Currently, many RISC-V companies are not profitable and still need to continue financing.” Dai Weimin pointed out a company that has consistently remained profitable—Nanjing Qinheng Microelectronics. “I think you have a good chance of going public on the Science and Technology Innovation Board; can you talk about how Qinheng has maintained profitability in the RISC-V field?”
Nanjing Qinheng Microelectronics’ Technical Director and Board Member, Yang Yong, took this question, stating that in the RISC-V wave, Qinheng has always chosen a differentiated route. “While others rush towards the stars and the sea, we are deeply rooted in the capillaries. Qinheng chooses to vertically cultivate ‘MCU + connectivity’—covering interfaces, baseband, RF, and Type-C all at once. After the first RISC-V chip was released in 2020, we pushed for two-line debugging, and the market responded; we then iterated to single-line and adaptive debugging, with profits feeding back into R&D, forming a closed loop. In the coming years, we will continue to cultivate this small plot of land meticulously.”
Yang Yong, Technical Director and Board Member of Nanjing Qinheng Microelectronics
Similarly, Yiswei, although it has only recently entered RISC-V, is flourishing and reportedly also in a profitable state. When discussing the “always-on, ultra-low power, ultra-light” application areas, He Ning, Senior Vice President and CTO of Yiswei Computing, believes that the areas where RISC-V will land first must meet three criteria—there must be new demands or demand iterations, the advantages of energy efficiency and customization must be leveraged, and the software ecosystem should not require too much additional work.
He Ning, Senior Vice President and CTO of Yiswei Computing
There have been cases showing that Yiswei has optimized energy efficiency through RISC-V, extending the battery life of button batteries from two years to ten years, with customers directly voting with orders, allowing Yiswei to quickly capture market share. He Ning emphasized that RISC-V needs to seize the window period of “demand changes + ecological adaptation,” and it is best to do so under the premise that the software ecosystem does not require too much additional work, as software integration is actually more challenging than hardware.
RISC-V’s Breakthrough in Autonomous Driving—How Open Architecture Restructures Automotive Chips
In recent years, most companies benefiting from AI have concentrated on the “trunk”; to allow more original manufacturers and end enterprises to reap the AI dividends, it is essential to let this big tree branch out. This involves the issue of the “end.” Speaking of the end, it is not only mobile phones and computers, watches and glasses, but also cars, which are one of the most important “ends.”
So what advantages does RISC-V have in high-level computing solutions for autonomous driving/ADAS? What is the current development status and prospects?
At the end of 2022, the American chip startup Ventana Micro Systems announced the launch of its Veyron series of high-performance RISC-V processors. According to the team, as the highest-performing RISC-V processor globally at the time, the first chip in the series, Veyron V1, uses a 5nm process and operates at a frequency of 3.6GHz, comparable to the latest existing processors for data centers, automotive, 5G, artificial intelligence, and client applications.
In 2023, the domestic RISC-V CPU IP company Chiplet Technology announced that its NA series CPU IP NA900 has obtained the ISO26262 highest automotive functional safety level ASIL D product certification. This means that NA900 is the world’s first RISC-V CPU IP product to obtain ISO26262 ASIL-D certification, making Chiplet Technology the third globally (after ARM and Synopsys) and the first domestic CPU IP provider to obtain automotive ISO 26262 ASIL D product certification.
Hu Zhenbo, founder of Chiplet Technology, pointed out that the automotive industry has long relied on proprietary architectures, leading to a fragmented software ecosystem. RISC-V, as an international standard instruction set architecture, can connect “islands” to establish a unified software architecture, avoiding reliance on a single IP supplier and depending on the entire industry ecosystem. This is the biggest prerequisite for its implementation in the automotive field. “Autonomous driving and ADAS require strong computing power, and the general software ecosystem does not have high requirements, so RISC-V’s advantages in AI can be leveraged here, and its automotive certification development is also promising. Combined with software ecology, hardware computing power, etc., it has comprehensive advantages and can be implemented in various automotive chip application fields.”
Is there an EDA ecosystem for RISC-V?
The discussion finally returned to a very practical question—does a so-called RISC-V EDA ecosystem currently exist? How mature are the RISC-V toolchain and verification platform? How do they differ from the EDA tools used for the Arm ecosystem?
Zhang Chunlin, Technical Executive Director of Synopsys, stated that compared to Arm or x86, RISC-V has gaps in testing sets. The industry has complete compatibility and benchmark testing for Arm, while RISC-V-related testing is relatively lacking. Additionally, RISC-V has many customized instruction sets, and companies need to conduct a lot of engineering work based on open-source customization. He suggested that the RISC-V Foundation accelerate the establishment of extended instruction set standards.
He Peixin, CTO of Hejian Technology, also emphasized the importance of RISC-V. He believes that RISC-V is an open architecture, and the effects of code modifications need to be verified in advance for hardware-software co-performance and functionality. Hejian Technology has already started related work to predict performance and functional risks before chip tape-out. Furthermore, the openness of RISC-V combined with chiplets can achieve different functionalities through various combinations. Hejian Technology is also developing tools to help customers decide on chiplet-related configurations (such as DIE process selection, Chiplet combinations).
Conclusion
In conclusion, Dai Weimin summarized, “The openness of the RISC-V ecosystem, its architectural customization capabilities, and the potential for software unification are key to its breakthroughs in AI, automotive, low-power, and other scenarios. However, the maturity of the ecosystem chain remains a shortcoming. Enterprises are driving technology implementation through differentiated paths (such as Tenstorrent’s ‘Baby RISC-V’ and Qinheng’s vertical cultivation), while also needing to address the shortcomings in the toolchain and testing sets to accelerate ecosystem maturity. In the future, it is necessary to build an ecosystem similar to CUDA through standardization, open-source IP sharing, and software stack unification, achieving a long-term competition with Arm, x86, and CUDA.”