1 SoC Verification
1.1 Flow
First, understand the chip based on the structure of the SPEC/DUT;
The basic chip generally consists of the following parts – just mindlessly existing basic parts:
Verification strategy:
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Black-box verification — Gray-box verification — White-box verification; I won’t elaborate on what they are;
White-box verification: For me, it means directly writing assertions;
Black-box verification: It simply means building a platform to inject stimuli;
Gray-box verification: As the test cases are continuously debugged, the understanding of the DUT’s internals also deepens; this is a process;
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Hierarchy division: ST — IT — UT; Essentially, it is based on the granularity division;
1.2 Verification Platform
Generally, it is: UVM + SV + C; here C: is the execution language of the processor; and the DPI-C interface;
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Verification Test Points
Spec –> Feature –> Test Point
Consider the following perspectives:
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Functional: Clock, Reset, Power, Register Access, FIFO Regular Points, Exception Handling, etc.;
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White-box test points:
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Interface:
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Scenario:
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Performance: Can the bandwidth meet the requirements?
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Exception:
2 Verification Functional Points
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Typical Values
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Boundary Values
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Exception Values
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Cross Values
Generally, there are specific Excel templates in the company to help open up ideas.
1.3 Execution Cases
Write test cases and execute debug
Regression Testing
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Ensure random opening can trigger issues;
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Used to iterate coverage; -cm line + cond + fsm + tgl; Common tools: DVE and VERDI;
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Ensure confirmation of RTL modifications;
Functional Coverage
Functional coverage measures whether all functions of the design have been implemented;
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Functional coverage is closely related to functional design, while code coverage only measures the execution of the design;
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If a certain functional judgment is not tested, code coverage cannot determine it, but functional coverage can; low functional coverage with high code coverage indicates an incomplete verification plan;
Understanding DUT Architecture
Use the DUT architecture diagram in the Spec to better understand the operation of the entire SoC chip;
Building the Verification Environment — UVM Verification Platform
UVM is a fixed verification methodology — verification components; it is convenient for reuse and direct inheritance;