Cortex-M3 DesignStart FPGA for Xilinx: A Comprehensive Guide

What is the ARM DesignStart program?

In 2010, ARM launched theARM DesignStart program, opening up the physical layout of over 1000 IPs. In 2015, the Cortex-M0 IP evaluation version was open-sourced, in 2017, the Cortex-M3 IP was open-sourced, and in 2018, the Cortex-A5 IP was open-sourced, providing users with a quick way to acquire ARM IP. Through the provided CPU and IP solutions, users can achieve customized SoCs more simply, quickly, and with lower risk.

The DesignStart program allows users to start designing and manufacturing SoCs based on the Cortex-M0 and Cortex-M3 processors without prepaying licensing fees, and only pays royalties after the product is successfully mass-produced.

The ARM Cortex-M0 and Cortex-M3 are the most widely used ARM processor cores globally, with a combined shipment of over 20 billion.

The DesignStart includes multiple versions, such as the Eval and FPGA versions for individuals, the Physical and Pro versions for enterprise users, and the University version for research and education. Let’s take a closer look at the differences.

1. DesignStart Eval Version

The evaluation board IP core can be freely applied for Cortex-M0 and Cortex-M3 processors and their subsystem IP through the official website. Internally, it is netlist-level Verilog code, which is not very readable.

2. DesignStart FPGA Version

The FPGA version is free to apply for and optimized for FPGA, which can be used in the development environment as an IP core. Currently, it only supports Xilinx and Gowin development environments and can be used for evaluation, teaching, and research.

With ARM development tools like Keil and Jlink, after implementing the ARM soft core on FPGA, you can use FPGA as an ARM core microcontroller, just like using a general MCU.

3. DesignStart Pro Version

The professional version is aimed at enterprise users who wish to develop ARM core chips. After completing registration on the official website, you need to sign a License authorization document, and then you will receive RTL-level Verilog code, which can be used to customize SoCs, such as function enhancement, performance improvement, etc.,without prepaying licensing fees, and royalties are charged only after the product is successfully launched.

The Cortex-M0 and Cortex-M3 processorsdo not require payment of licensing fees. The Cortex-A5 processor requires a very low licensing fee and can provide up to 3 years of technical support.

4. DesignStart Physical & University Version

The physical implementation IP version can accelerate the physical layout design of chips, while the university program version is used for research and education in SoC design.

Cortex-M3 Xilinx FPGA Soft Core Download

Users can use the Xilinx Vivado environment to build a custom ARM Cortex-M0 or Cortex-M3 core SoC on FPGA. The ARM DesignStart program provides the processor core, and by adding the AXI bus, more AXI peripherals can be added, such as GPIO, UART, SPI, TIMER, INTC, etc.

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