Differences in SysTick Usage Between Cortex-M3 and Cortex-M85 Microcontrollers
Getting Started with Cortex-M3: Overview of the Architecture
Click the card below to follow Arm Technology Academy
This article is selected from the "Arm Technology Blog" column, originally from Zhihu. This series will guide you to learn about the Cortex-M3, including its architecture design, register composition, concepts of clock and bus, functions and usage of various peripherals, etc.
Original article: https://zhuanlan.zhihu.com/p/52235675
The Getting Started with Cortex-M3 guide is a new series of articles in this column, focusing on explaining the architecture design, register composition, concepts of clock and bus, functions and
Key Concepts of Cortex-M3
Thread mode: This mode is active when the processor is reset or exits from an exception. The code in this mode can be either privileged or user code, controlled by CONTROL[0].
Handler mode: This mode is entered when an exception (including interrupts) occurs, and all code in this mode has privileged access.
Privileged access: Complete access rights to processor resources; this access mode is entered after a processor reset; zeroing CONTROL[0] enters user mode.
User access:
Comprehensive Guide to ARM Cortex-M3 GPIO Interface
1、GPIO Structure and Registers
GPIO includes multiple 16-bit I/O ports, each of which can independently set 3 types of input modes and 4 types of output modes, and can be independently set or reset.
GPIO consists of registers, input drivers, output drivers, and other components, as shown in the figure below.
GPIO operates through 7 32-bit registers:
The 4 configuration