On August 14, technology media Tom’s Hardware reported that the American startup Normal Computing has successfully taped out the CN101, which is the world’s first thermodynamic computing chip.
Note: Thermodynamic computing is a new computing paradigm that utilizes the thermal noise and randomness of physical systems to perform calculations, achieving computational results by reaching a state of thermal equilibrium in the system, suitable for non-deterministic algorithms; tape-out refers to the milestone of delivering the circuit design for manufacturing after the chip design is completed, marking the end of the design phase and the beginning of the trial production process.
This chip is specifically designed for AI and high-performance computing (HPC) data centers, aiming to address the bottlenecks in energy efficiency and computational power scaling faced by current chips, replacing traditional silicon-based computing models, primarily relying on thermodynamics and randomness mechanisms.
Unlike traditional chips, thermodynamic chips do not reject noise; instead, they utilize it as a computational resource. The chip components initially exist in a semi-random state, and after inputting a program, the system reaches thermal equilibrium, with its stable state representing the computational result.
This mechanism is suitable for non-deterministic algorithms in AI training, such as sampling, image generation, and linear algebra operations. Zachary Belatche, the silicon engineering lead at Normal, pointed out that such algorithms cover multiple fields, including scientific computing and artificial intelligence, with enormous potential.
The CN101 chip focuses on efficiently executing matrix operations and linear algebra tasks, integrating Normal’s self-developed sampling system to accelerate probabilistic computations. According to the company, its energy efficiency can reach 1000 times that of traditional chips under specific AI training loads.
Normal Computing’s long-term vision is to build heterogeneous computing servers that integrate CPU, GPU, thermodynamic ASICs, probabilistic chips, and even quantum chips, allowing each type of problem to match the optimal computing architecture. Its CN series chip roadmap includes iterative versions planned for 2026 and 2028, aiming to support deeper and more frequent use of image and video diffusion models.
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