In today’s processor world, from tiny IoT nodes to smartphones and large data center servers, ARM processors have captured a significant share of the market due to their excellent energy efficiency. ARM’s unique business model (focusing on chip architecture design and licensing rather than manufacturing) has enabled numerous semiconductor companies worldwide to develop various processor products based on its architecture, collectively building a prosperous, open, and vibrant technology ecosystem.

Throughout the long history of ARM architecture development, processor models have typically been named with incrementing numbers, such as the classic ARM7, ARM9, and ARM11 series. Since the implementation of ARMv6 is ARM11, it would be logical for the implementation of ARMv7 to be called ARM12. However, ARM deliberately chose not to use the name ARM12, instead adopting the new series name Cortex instead. When Cortex was released, an ARM executive stated, “Not calling it ARM12 was to emphasize that this is a completely new series.”

This is not just a name change; it marks a profound shift in ARM’s product strategy. The name Cortex (Cortex) signifies the ambition of ARM to create the industry’s top central processing units. The deeper reason is that the ARMv7 architecture is no longer a single design but has been strategically segmented to meet different market demands, with the Cortex brand serving as the vehicle for this strategy.

ARM has defined three sub-series for ARMv7 based on various application domains:

• ARMv7-M, optimized for the microcontroller domain, corresponding to the Cortex-M series

• ARMv7-R, optimized for real-time processing, corresponding to the Cortex-R series

• ARMv7-A, continuing and enhancing traditional rich application domains, corresponding to the Cortex-A series

The division of these three Cortex sub-series uses the corresponding initials of Microcontroller, Real-time, and Application, and interestingly, the letters “A, R, M” connect to form the name ARM, indicating that there is indeed a method to ARM’s naming strategy.

As the legitimate successor to classic processors like ARM7/9/11, the Cortex-A series targets performance-intensive application domains. It supports complete operating system support (such as Linux, Android), complex memory management units (MMUs), and powerful computing capabilities, making it the core of high-end applications such as smartphones, tablets, servers, and network devices.

The Cortex-R series is designed for scenarios with stringent real-time and reliability requirements. For example, automotive braking systems, hard drive controllers, and 5G baseband chips. These processors feature tightly coupled memory (TCM) and fault detection mechanisms, ensuring tasks can be completed within predictable timeframes, making them ideal for high-reliability embedded systems.

The birth of the Cortex-M series marks ARM’s comprehensive entry into the microcontroller (MCU) market. To provide the most competitive solutions in the vast and diverse MCU market, Cortex-M strategically removed unnecessary complex features like MMUs found in traditional MCU applications, focusing on achieving extreme low power consumption, low cost, and high energy efficiency, which has also achieved great success.

Instruction Set Architecture (ISA) and Microarchitecture

To understand any processor, it is essential to distinguish between two core concepts:Instruction Set Architecture (ISA) and Microarchitecture. Together, these define a processor’s capabilities and characteristics.

Instruction Set Architecture (ISA): is the interface specification between the processor and software, defining the instruction set, registers, data types, memory model, exception and interrupt handling, etc., that the processor can understand and execute. It concerns “what to do”. For example, <span>ARMv7-A</span>, <span>ARMv8-A</span>, and <span>ARMv9-A</span> are different generations of ISA. The primary goal of ISA is to ensure software compatibility and ecosystem stability. ISA compatibility is the cornerstone of the software ecosystem, allowing programs written for a specific ISA (without operating system abstraction) to run directly on all processors implementing that ISA. For instance, any processor implementing the ARMv9-A architecture, whether designed by ARM itself or developed by Apple or Qualcomm, must correctly execute any software compiled for ARMv9-A.

Microarchitecture: is the specific physical implementation of the ISA, relating to the internal circuit design of the processor, such as pipeline stages, cache sizes, branch predictor algorithms, and the number of execution units. It determines “how to do” and “how fast to do it”. The primary goal of microarchitecture is to achieve the best balance between performance, power consumption, and area (PPA), which is the core battleground for chip companies. Examples of microarchitecture implementations include ARM’s own Cortex-X4; Apple’s custom-designed Everest (M2 high-performance core); and Qualcomm’s custom-designed Oryon. They may all implement the same ARMv9-A ISA, but their internal designs can be vastly different.

ARM builds its vast ecosystem through two modes: licensing its ISA (which allows for self-developed microarchitecture after obtaining a license) and microarchitecture IP (directly providing Cortex core designs). ISA ensures the unity and prosperity of the entire ARM ecosystem, while differentiated designs of microarchitecture provide a platform for major chip giants to compete and showcase their technological prowess.

Top companies like Apple and Qualcomm obtain ARM’s ISA license, then invest hundreds or even thousands of top engineers, spending billions of dollars to design their unique microarchitecture from scratch, achieving deep optimization.

Through the licensing of microarchitecture, companies like Qualcomm, MediaTek, Samsung, NXP, TI, Rockchip, Allwinner, and Broadcom can build their SoC products by selecting different Cortex microarchitectures, creating a large and competitive semiconductor ecosystem, with these SoC products maintaining a relatively open market strategy.

For example, Rockchip, based on ARM’s Cortex microarchitecture licensing, has designed SoC products like RK3506 (3-core [email protected] + Cortex-M0), RK3562 (4-core Cortex-A53@2GHz + 1T computing power NPU), and RK3576 (4-core [email protected] + 4-core Cortex-A53@2GHz + 6T computing power NPU).

Based on Rockchip’s SoC, we also have various domestic industrial evaluation boards launched by Chuanglong Technology that can be quickly developed.

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ARM’s open licensing model has created a vibrant and competitive “tropical rainforest” ecosystem, giving rise to countless low-cost, highly integrated SoC species that adapt to various environments. This fertile ground perfectly nurtures a diverse and function-rich board market. Developers can find evaluation boards tailored to specific needs, rapidly bringing products to market.

The Evolution of Instruction Sets

ARMv7-A: The King of the 32-bit Era

ARMv7-A is the cornerstone of the early success of the Cortex-A series, being a 32-bit ISA. It introduced NEON SIMD (Single Instruction Multiple Data) extensions, significantly enhancing multimedia processing capabilities. Meanwhile, the introduction of Thumb-2 instruction set achieved an excellent balance between performance and code density by mixing 16-bit and 32-bit instructions, dominating the entire 32-bit mobile computing era.

ARMv8-A: The Revolution Towards 64-bit

ARMv8-A represents a revolutionary leap in ARM architecture, fully introducing 64-bit computing capabilities to address the addressing needs of over 4GB of memory and more complex computational loads. It includes two execution states:

• AArch64: Provides 64-bit processing capabilities, with a larger virtual address space and up to 31 general-purpose registers, designed for modern high-performance computing.

• AArch32: Used for backward compatibility, allowing seamless execution of 32-bit code written for ARMv7-A, ensuring a smooth transition for the ecosystem.

ARMv9-A: A New Era Focused on AI and Security

As the largest architectural upgrade in nearly a decade, ARMv9-A builds on ARMv8-A, focusing on three key areas: Security, AI and Vector Computing, Performance.

• Confidential Compute Architecture (CCA): Introduces the Realm Management Extension (RME), creating a hardware-isolated “Realm” beyond the existing secure world and normal world. Applications can run in the Realm, inaccessible even to the operating system or hypervisor, providing unprecedented data security and privacy protection.

• Second Generation Scalable Vector Extension (SVE2): As the successor to NEON, SVE2 offers more powerful and flexible vector processing capabilities. It allows vector lengths to be selected between 128 bits and 2048 bits in increments of 128 bits, enabling software developers to write vectorized code independent of hardware implementation, greatly enhancing computational performance in machine learning (ML), digital signal processing (DSP), and multimedia.

• Memory Tagging Extension (MTE): To address long-standing memory safety issues in the software industry (such as buffer overflows), MTE attaches a small tag to each 16-byte block of memory and embeds the same tag in pointers. During memory access, the processor checks if the two match; if not, it immediately raises an exception, efficiently detecting and preventing memory safety vulnerabilities at the hardware level.

ARMv9-A is not merely a “performance upgrade” but a “restructuring of architecture” aimed at meeting computing demands for the next 5-10 years—by solidifying the foundation for AI and HPC through the SVE2 instruction set, building a multi-layered defense system through the RME security domain, and achieving a balance between performance and power consumption through “dynamic energy efficiency optimization,” ultimately achieving full-scene coverage from edge (phones, cars) to cloud (servers).

The Evolution of Cortex-A Cores

By analyzing representative Cortex-A cores from the ARMv7 to ARMv9 era, we can clearly see ARM’s evolving path of balancing performance, power consumption, and area (PPA).

The table below summarizes the key features of each major core:

Processor Core	ARM ISA	Bit Width	Target Usage	Release Year (Approx.)	Key Features
Cortex-A8	ARMv7-A	32	Single-core Performance	2005	The first ARMv7-A processor, ARM’s first superscalar
Cortex-A9	ARMv7-A	32	Performance and Power Balance	2007	The first out-of-order multi-core, the mainstay of the mobile era
Cortex-A7	ARMv7-A	32	High-efficiency LITTLE core	2011	The classic “LITTLE” core in big.LITTLE
Cortex-A15	ARMv7-A	32	High-performance big core	2010	The classic “big” core in big.LITTLE
Cortex-A53	ARMv8-A	64	High-efficiency LITTLE core	2012	The long-dominant 64-bit high-efficiency core
Cortex-A57	ARMv8-A	64	High-performance big core	2012	The first batch of 64-bit high-performance cores
Cortex-A72	ARMv8-A	64	High-performance big core	2015	A57’s power-optimized version, a classic of its generation
Cortex-A55	ARMv8.2-A	64	High-efficiency LITTLE core	2017	The high-efficiency core of the DynamIQ era
Cortex-A75	ARMv8.2-A	64	High-performance big core	2017	The performance core of the DynamIQ era
Cortex-A78	ARMv8.2-A	64	Balanced big core	2020	A model of PPA balance
Cortex-X1	ARMv8.2-A	64	Extreme performance super big core	2020	The pioneering project of Cortex-X
Cortex-A510	ARMv9-A	64	High-efficiency small core	2021	The first ARMv9 high-efficiency core, adopting a merged core design
Cortex-A710	ARMv9-A	64	Balanced big core	2021	The first ARMv9 high-performance big core
Cortex-X2	ARMv9-A	64	Extreme performance super big core	2021	The successor to X1, focusing on single-core performance
Cortex-A520	ARMv9.2-A	64	High-efficiency small core	2023	Removed 32-bit support, focusing on 64-bit efficiency
Cortex-A720	ARMv9.2-A	64	Balanced big core	2023	Mainstream performance core, balancing area and performance
Cortex-X4	ARMv9.2-A	64	Extreme performance super big core	2023	Aiming for higher frequencies and IPC
Cortex-A725	ARMv9.2-A	64	High-performance big core	2024	Successor to A720, with a 25% efficiency improvement
Cortex-X925	ARMv9.2-A	64	Extreme performance super big core	2024	Codename “Blackhawk”, 3nm process, performance beast

Selection Reference

Selection for Industrial Control and HMI

For good performance and stability, classic Cortex-A7 or modern cores that balance performance and efficiency like Cortex-A55 are good choices.

Cortex-A7 is designed to provide moderate performance with minimal power consumption and core area. Its key features include:

• High-efficiency Design: As ARM’s most efficient application processor at the time, a single Cortex-A7 core’s efficiency is five times that of Cortex-A8, while its size is only one-fifth, with significant performance improvements.

• Ordered, Partially Dual-Issue Pipeline: Cortex-A7 employs a relatively simple 8-stage in-order execution pipeline architecture, which helps reduce power consumption and chip area.

• ARMv7-A Architecture: It implements the ARMv7-A instruction set architecture and is fully compatible with the high-performance Cortex-A15, which is the basis for achieving seamless switching in big.LITTLE. This includes support for NEON SIMD extensions, VFPv4 floating-point units, hardware virtualization, large physical address extensions (LPAE), and other features.

• Configurable Multi-core: Supports configurations from single-core to up to eight cores, providing flexible options for different devices.

• Integrated L2 Cache: The integrated L2 cache (up to 1MB) enhances memory system performance, with over 20% performance improvement compared to previous generations.

Selection for IoT and Deep Embedded Systems

For applications that are extremely sensitive to power consumption and cost, Cortex-A53 or its modern successors Cortex-A510 / A520 are ideal choices. They provide sufficient 64-bit performance to run systems like Linux while maintaining extremely low power consumption.

Cortex-A53 is designed to replace the popular 32-bit Cortex-A7 processor, providing higher performance while maintaining extremely low power consumption.

Cortex-A53 achieves a delicate balance between efficiency, performance, and area, with key features including:

• ARMv8-A Architecture and 64-bit Computing: Cortex-A53 is the pioneer of ARM’s transition to 64-bit computing. It implements the new ARMv8-A instruction set, capable of running in both 64-bit (AArch64) and 32-bit (AArch32) execution states, ensuring backward compatibility with existing 32-bit applications. The 64-bit architecture brings a larger virtual address space and more general-purpose registers, which are crucial for handling large-scale data and complex computations.

• High-efficiency Design: As ARM’s most efficient application processor at the time, Cortex-A53 outperforms Cortex-A9 in the same process while significantly reducing power consumption and area. Its design focuses on providing powerful computing capabilities in power-constrained environments.

• Ordered, Dual-Issue Pipeline: Cortex-A53 features an 8-stage in-order execution pipeline and is a dual-issue superscalar design, capable of decoding and issuing multiple instructions simultaneously, representing a significant advancement over Cortex-A7’s single-issue capability.

• Configurable Multi-core: Cortex-A53 supports flexible configurations from single-core to up to four cores (even reaching eight cores in some designs), with each core having its own L1 cache and sharing an L2 cache.

• Integrated NEON and VFPv4: Each core is mandatorily integrated with advanced SIMD (NEON) and VFPv4 floating-point units, significantly enhancing performance for multimedia and signal processing tasks.

Selection for Performance Computing

DynamIQ architecture’s “big core + big core + little core” three-tier structure is the current mainstream design. Flagship devices typically use the latest Cortex-X + Cortex-A7xx + Cortex-A5xx combination. The big.LITTLE architecture used in Rockchip’s RK3576 is also a good choice.RK3576’s“big” part features4 Cortex-A72 high-performance cores for handling compute-intensive tasks, such as running complex applications, processing high-definition user interfaces, gaming, or performing complex algorithm calculations.RK3576’s“LITTLE” part consists of4 Cortex-A53 high-efficiency cores, which have extremely low power consumption, responsible for handling lighter background tasks, system standby, audio playback, or simple daily operations.

This “4 big cores + 4 little cores” configuration is a very mature and successful design by Rockchip. RK3576 can be seen as a powerful upgrade of the classic model RK3399 (2x A72 + 4x A53), doubling the number of big cores and pairing them with a more powerful NPU (up to 6 TOPS) and other peripherals.

For those needing to quickly evaluate Cortex-A processing, they can check out the evaluation board products from Chuanglong Technology.

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